20 Jul
2015
20 Jul
'15
11:11 p.m.
On 06/29/2015 12:49 AM, Alison Wang wrote:
From: Zhichun Hua zhichun.hua@freescale.com
For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit position [13:12] of TCR_ELx register.
Signed-off-by: Zhichun Hua zhichun.hua@freescale.com Signed-off-by: York Sun yorksun@freescale.com
Applied to u-boot-fsl-qoriq master branch.
York