On 06/08/2012 23:34, Marek Vasut wrote:
The SPL doesn't need the CP15 reconfiguration, as that's what the BootROM does for us already. Moreover, when the CP15 is reconfigured and the code returns control to BootROM, the USB boot works no more.
Remove the code and allow [1] to work properly as well.
[1] http://git.bfuser.eu/?p=marex/mxsldr.git;a=summary
Signed-off-by: Marek Vasut marex@denx.de Cc: Stefano Babic sbabic@denx.de Cc: Fabio Estevam fabio.estevam@freescale.com
arch/arm/cpu/arm926ejs/mx28/start.S | 42 ----------------------------------- 1 file changed, 42 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx28/start.S b/arch/arm/cpu/arm926ejs/mx28/start.S index e572b78..7ccd337 100644 --- a/arch/arm/cpu/arm926ejs/mx28/start.S +++ b/arch/arm/cpu/arm926ejs/mx28/start.S @@ -180,14 +180,6 @@ _reset: orr r0,r0,#0xd3 msr cpsr,r0
- /*
* we do sys-critical inits only at reboot,* not when booting from ram!*/-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
bl board_init_ll
/*
@@ -207,40 +199,6 @@ _reset: pop {r0-r12,r14} bx lr
-/*
- CPU_init_critical registers
- setup important registers
- setup memory timing
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT -cpu_init_crit:
- /*
* flush v4 I/D caches*/- mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
- /*
* disable MMU stuff and caches*/- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
- bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
- orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
- mcr p15, 0, r0, c1, c0, 0
- mov pc, lr /* back to my caller */
- .align 5
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
_hang: ldr sp, _TEXT_BASE /* switch to abort stack */ 1:
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic