The SEC driver code has been cleaned up to work for 64 bit physical addresses and systems where endianess of SEC block is different from the Core. Changes: 1. Descriptor created on Core is modified as per SEC block endianness before the job is submitted. 2. The read/write of physical addresses to Job Rings are done using I/O functions defined for SEC which will take care of the endianness. 3. The 32 bit low and high part of the 64 bit address in descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal aneesh.bansal@freescale.com --- Changes in v2: sec_out_phys and sec_in_phys has been defined in fsl_sec.h to do two 32 bit write or read opeartions. The low and high part of the 32 bit address will depend on endianness of CAAM Block.
drivers/crypto/fsl/desc_constr.h | 24 ++++++++++++++++++++++++ drivers/crypto/fsl/jr.c | 32 ++++++++++++++++++++++---------- drivers/crypto/fsl/jr.h | 3 +-- include/fsl_sec.h | 28 ++++++++++++++++++++++++++++ 4 files changed, 75 insertions(+), 12 deletions(-)
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index f9cae91..ac4a933 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -36,6 +36,21 @@ LDST_SRCDST_WORD_DECOCTRL | \ (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
+#ifdef CONFIG_PHYS_64BIT +union ptr_addr_t { + u64 m_whole; + struct { +#ifdef CONFIG_SYS_FSL_SEC_LE + u32 low; + u32 high; +#else + u32 high; + u32 low; +#endif + } m_halfs; +}; +#endif + static inline int desc_len(u32 *desc) { return *desc & HDR_DESCLEN_MASK; @@ -65,7 +80,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr) { dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+#ifdef CONFIG_PHYS_64BIT + /* The Position of low and high part of 64 bit address + * will depend on the endianness of CAAM Block */ + union ptr_addr_t ptr_addr; + ptr_addr.m_halfs.high = (u32)(ptr >> 32); + ptr_addr.m_halfs.low = (u32)ptr; + *offset = ptr_addr.m_whole; +#else *offset = ptr; +#endif
(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ; } diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 17392c9..07b97e8 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -11,6 +11,7 @@ #include "fsl_sec.h" #include "jr.h" #include "jobdesc.h" +#include "desc_constr.h"
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) @@ -154,11 +155,25 @@ static int jr_hw_reset(void)
/* -1 --- error, can't enqueue -- no space available */ static int jr_enqueue(uint32_t *desc_addr, - void (*callback)(uint32_t desc, uint32_t status, void *arg), + void (*callback)(uint32_t status, void *arg), void *arg) { struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; int head = jr.head; + uint32_t desc_word; + int length = desc_len(desc_addr); + int i; + + /* The descriptor must be submitted to SEC block as per endianness + * of the SEC Block. + * So, if the endianness of Core and SEC block is different, each word + * of the descriptor will be byte-swapped. + */ + for (i = 0; i < length; i++) { + desc_word = desc_addr[i]; + sec_out32((uint32_t *)&desc_addr[i], desc_word); + } + dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
if (sec_in32(®s->irsa) == 0 || @@ -166,7 +181,6 @@ static int jr_enqueue(uint32_t *desc_addr, return -1;
jr.info[head].desc_phys_addr = desc_phys_addr; - jr.info[head].desc_addr = (uint32_t)desc_addr; jr.info[head].callback = (void *)callback; jr.info[head].arg = arg; jr.info[head].op_done = 0; @@ -177,7 +191,7 @@ static int jr_enqueue(uint32_t *desc_addr, ARCH_DMA_MINALIGN); flush_dcache_range(start, end);
- jr.input_ring[head] = desc_phys_addr; + sec_out_phys(&jr.input_ring[head], desc_phys_addr); start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); @@ -195,7 +209,7 @@ static int jr_dequeue(void) int head = jr.head; int tail = jr.tail; int idx, i, found; - void (*callback)(uint32_t desc, uint32_t status, void *arg); + void (*callback)(uint32_t status, void *arg); void *arg = NULL;
while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) { @@ -208,14 +222,12 @@ static int jr_dequeue(void)
found = 0;
- dma_addr_t op_desc = jr.output_ring[jr.tail].desc; - uint32_t status = jr.output_ring[jr.tail].status; - uint32_t desc_virt; + dma_addr_t op_desc = sec_in_phys(&jr.output_ring[jr.tail].desc); + uint32_t status = sec_in32(&jr.output_ring[jr.tail].status);
for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) { idx = (tail + i) & (jr.size - 1); if (op_desc == jr.info[idx].desc_phys_addr) { - desc_virt = jr.info[idx].desc_addr; found = 1; break; } @@ -244,13 +256,13 @@ static int jr_dequeue(void) sec_out32(®s->orjr, 1); jr.info[idx].op_done = 0;
- callback(desc_virt, status, arg); + callback(status, arg); }
return 0; }
-static void desc_done(uint32_t desc, uint32_t status, void *arg) +static void desc_done(uint32_t status, void *arg) { struct result *x = arg; x->status = status; diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 1526060..5f15ed5 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -42,9 +42,8 @@ struct op_ring { } __packed;
struct jr_info { - void (*callback)(dma_addr_t desc, uint32_t status, void *arg); + void (*callback)(uint32_t status, void *arg); dma_addr_t desc_phys_addr; - uint32_t desc_addr; uint32_t desc_len; uint32_t op_done; void *arg; diff --git a/include/fsl_sec.h b/include/fsl_sec.h index abc62da..9f344a8 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -28,6 +28,34 @@ #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined #endif
+#ifdef CONFIG_PHYS_64BIT +#ifdef CONFIG_SYS_FSL_SEC_LE + +#define sec_in_phys(addr) \ + ((u64)sec_in32((u32 *)(addr) + 1) << 32) | \ + (sec_in32((u32 *)(addr))) + +#define sec_out_phys(addr, val) \ + sec_out32((u32 *)(addr) + 1, (u32)((val) >> 32)); \ + sec_out32((u32 *)(addr), (u32)(val)) + +#elif defined(CONFIG_SYS_FSL_SEC_BE) + +#define sec_in_phys(addr) \ + ((u64)sec_in32((u32 *)(addr)) << 32) | \ + (sec_in32((u32 *)(addr) + 1)) + +#define sec_out_phys(addr, val) \ + sec_out32((u32 *)(addr), (u32)((val) >> 32)); \ + sec_out32((u32 *)(addr) + 1, (u32)(val)) + +#else +#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined +#endif +#else +#define sec_out_phys sec_out32 +#define sec_in_phys sec_in32 +#endif /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* RNG4 TRNG test registers */