On Fri, 2012-01-27 at 08:09 -0700, Tom Rini wrote:
On Fri, Jan 27, 2012 at 8:05 AM, Robert Nelson robertcnelson@gmail.com wrote:
On Thu, Jan 26, 2012 at 5:21 PM, Tom Rini tom.rini@gmail.com wrote:
On Thu, Jan 26, 2012 at 12:35 PM, wilsonjonathan piercing_male@hotmail.com wrote:
On Thu, 2012-01-26 at 12:28 -0700, Tom Rini wrote:
On Thu, Jan 26, 2012 at 12:14 PM, wilsonjonathan piercing_male@hotmail.com wrote:
On Thu, 2012-01-26 at 10:08 -0700, Tom Rini wrote: > On Wed, Jan 25, 2012 at 1:06 PM, wilsonjonathan > piercing_male@hotmail.com wrote: > > The u-boot loader is showing an incorrect size in the memory, and > > passing the invalid information to the kernel. > > What revision of the board do you have? Is this a 'classic' rev C4? Thanks. > As far as I'm aware yes, standard C4 from digikey.
I've done a little more searching, and found that adding #define DEBUG to /arc/arm/lib/board.c brings up more detailed info.
I will re-confirm with mine then. Previous versions of U-Boot/MLO report how much memory, 512MB?
I don't have an older version to hand, but according to the specs it should be 256MB using a 2Gb MDDR SDRAM and I seem to recall it did display that.
OK, thanks. Does the following fix it for you?
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 5c04b34..1efdbb0 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -161,7 +161,7 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, case REVISION_C4: if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { /* 512MB DDR */
*mcfg = NUMONYX_V_MCFG_165(512 << 20);
*mcfg = NUMONYX_V_MCFG_165(256 << 20); *ctrla = NUMONYX_V_ACTIMA_165; *ctrlb = NUMONYX_V_ACTIMB_165; *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;Hi Tom,
No change on my c4:
OK, can you throw in some printfs to see which of the cases in that function your C4 is hitting? Thanks!
Hi. The text is wrong as well according to the Circuitco site.
I'm afraid I don't know diff but the code should say.
case REVISION_C4: if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { /* Beagleboard rev C5 ST-micro POP 512MB NAND */ *mcfg = NUMONYX_V_MCFG_165(512 << 20); *ctrla = NUMONYX_V_ACTIMA_165; *ctrlb = NUMONYX_V_ACTIMB_165; *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) { /* Beagleboard rev C4 micron POP, 256MB NAND */ *mcfg = MICRON_V_MCFG_200(256 << 20); *ctrla = MICRON_V_ACTIMA_200; *ctrlb = MICRON_V_ACTIMB_200; *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break;