This patch adds the a4m2k MPC5200B board port. Its a derivate of the a3m071 board with only minor changes.
Additionally this patch includes some clean-up changes: - Remove I2C support from a3m071 as its unused - Fix/enhance default env variables - Fix some comments - Add newly introduced CONFIG_SPL_TARGET to automatically build "u-boot-img.bin"
Signed-off-by: Stefan Roese sr@denx.de --- MAINTAINERS | 1 + board/a3m071/a3m071.c | 91 +++++++++++++++++++++++++++++++++--- board/a3m071/is46r16320d.h | 35 ++++++++++++++ boards.cfg | 1 + include/configs/a3m071.h | 112 ++++++++++++++++++++++++++------------------- 5 files changed, 186 insertions(+), 54 deletions(-) create mode 100644 board/a3m071/is46r16320d.h
diff --git a/MAINTAINERS b/MAINTAINERS index 428b006..e48288f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -389,6 +389,7 @@ Ricardo Ribalda ricardo.ribalda@uam.es Stefan Roese sr@denx.de
a3m071 MPC5200 + a4m2k MPC5200
P3M7448 MPC7448
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c index 89ced82..0a86e9a 100644 --- a/board/a3m071/a3m071.c +++ b/board/a3m071/a3m071.c @@ -24,10 +24,15 @@ #include <mpc5xxx.h> #include <pci.h> #include <miiphy.h> +#include <linux/compiler.h> #include <asm/processor.h> #include <asm/io.h>
+#ifdef CONFIG_A4M2K +#include "is46r16320d.h" +#else #include "mt46v16m16-75.h" +#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -63,6 +68,12 @@ static void sdram_start(int hi_addr)
/* normal operation */ out_be32((void *)MPC5XXX_SDRAM_CTRL, control); + + /* + * Wait a short while for the DLL to lock before accessing + * the SDRAM + */ + udelay(100); } #endif
@@ -157,12 +168,6 @@ static void get_revisions(int *failsavelevel, int *digiboardversion, struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; u8 val;
- /* - * Figure out failsavelevel - * see ticket dsvk#59 - */ - *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */ - /* read digitalboard-version from TMR[2..4] */ val = 0; val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0; @@ -170,6 +175,17 @@ static void get_revisions(int *failsavelevel, int *digiboardversion, val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0; *digiboardversion = val;
+ /* + * A4M2K only supports digiboardversion. No failsavelevel and + * fpgaversion here. + */ +#if !defined(CONFIG_A4M2K) + /* + * Figure out failsavelevel + * see ticket dsvk#59 + */ + *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */ + if (*digiboardversion == 0) { *failsavelevel = 1; /* digiboard-version ok */
@@ -183,6 +199,7 @@ static void get_revisions(int *failsavelevel, int *digiboardversion, if (*fpgaversion == 1) *failsavelevel = 2; /* fpga-version ok */ } +#endif }
/* @@ -196,6 +213,11 @@ void spl_board_init(void) struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; struct mpc5xxx_mmap_ctl *mm = (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; + +#if defined(CONFIG_A4M2K) + /* enable CS3 and CS5 (FPGA) */ + setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21)); +#else int digiboardversion; int failsavelevel; int fpgaversion; @@ -219,6 +241,7 @@ void spl_board_init(void)
/* And write new value back to register */ out_be32(&mm->ipbi_ws_ctrl, val); +#endif
/* * No need to change the pin multiplexing (MPC5XXX_GPS_PORT_CONFIG) @@ -234,6 +257,55 @@ void spl_board_init(void) */ setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, 1 << (31 - 0));
+#if defined(CONFIG_A4M2K) + /* Setup USB[x] as MPCDiag[0..3] GPIO outputs */ + + /* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */ + gpio->simple_ddr |= 1 << (31 - 15); + gpio->simple_ddr |= 1 << (31 - 14); + gpio->simple_ddr |= 1 << (31 - 13); + gpio->simple_ddr |= 1 << (31 - 12); + + /* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */ + gpio->simple_gpioe |= 1 << (31 - 15); + gpio->simple_gpioe |= 1 << (31 - 14); + gpio->simple_gpioe |= 1 << (31 - 13); + gpio->simple_gpioe |= 1 << (31 - 12); + + /* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */ + + /* set PSC2[0..2] (STSLED[0..2]) direction to output */ + gpio->simple_ddr |= 1 << (31 - 27); + gpio->simple_ddr |= 1 << (31 - 26); + gpio->simple_ddr |= 1 << (31 - 25); + + /* enable PSC2[0..2] (STSLED[0..2]) as GPIO */ + gpio->simple_gpioe |= 1 << (31 - 27); + gpio->simple_gpioe |= 1 << (31 - 26); + gpio->simple_gpioe |= 1 << (31 - 25); + + /* Setup PSC6[2] as MRST2 self reset GPIO output */ + + /* set PSC6[2]/IRDA_TX (MRST2) direction to output */ + gpio->simple_ddr |= 1 << (31 - 3); + + /* set PSC6[2]/IRDA_TX (MRST2) output as open drain */ + gpio->simple_ode |= 1 << (31 - 3); + + /* set PSC6[2]/IRDA_TX (MRST2) output as default high */ + gpio->simple_dvo |= 1 << (31 - 3); + + /* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */ + gpio->simple_gpioe |= 1 << (31 - 3); + + /* Setup PSC6[3] as HARNSSCD harness code GPIO input */ + + /* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */ + gpio->simple_ddr |= 0 << (31 - 2); + + /* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */ + gpio->simple_gpioe |= 1 << (31 - 2); +#else /* setup GPIOs for status-leds if needed - see ticket #57 */ if (failsavelevel > 0) { /* digiboard-version is OK */ @@ -267,7 +339,7 @@ void spl_board_init(void) * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above */ } - +#endif }
int checkboard(void) @@ -278,11 +350,16 @@ int checkboard(void)
get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
+#ifdef CONFIG_A4M2K + puts("Board: A4M2K\n"); + printf(" digiboard IO version %u\n", digiboardversion); +#else puts("Board: A3M071\n"); printf("Rev: failsave level %u\n", failsavelevel); printf(" digiboard IO version %u\n", digiboardversion); if (failsavelevel > 0) /* only if fpga-version red */ printf(" fpga IO version %u\n", fpgaversion); +#endif
return 0; } diff --git a/board/a3m071/is46r16320d.h b/board/a3m071/is46r16320d.h new file mode 100644 index 0000000..8183d81 --- /dev/null +++ b/board/a3m071/is46r16320d.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SDRAM_DDR /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */ + +/* SDRAM Config Standard timing */ +#define SDRAM_MODE 0x008d0000 +#define SDRAM_EMODE 0x40010000 +#define SDRAM_CONTROL 0x70430f00 +#define SDRAM_CONFIG1 0x33622930 +#define SDRAM_CONFIG2 0x46670000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/boards.cfg b/boards.cfg index 70a1569..56da76e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -475,6 +475,7 @@ cmi_mpc5xx powerpc mpc5xx cmi PATI powerpc mpc5xx pati mpl a3m071 powerpc mpc5xxx a3m071 a4m072 powerpc mpc5xxx a4m072 +a4m2k powerpc mpc5xxx a3m071 - - a3m071:A4M2K BC3450 powerpc mpc5xxx bc3450 canmb powerpc mpc5xxx cm5200 powerpc mpc5xxx diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index df3b4ae..6603e04 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -26,15 +26,22 @@ #define CONFIG_MPC5200 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_A3M071 /* ... on A3M071 board */ -#define CONFIG_MPC5200_DDR /* ... use DDR RAM */
#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
+#define CONFIG_SPL_TARGET "u-boot-img.bin" + #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
#define CONFIG_MISC_INIT_R #define CONFIG_SYS_LOWBOOT /* Enable lowboot */
+#ifdef CONFIG_A4M2K +#define CONFIG_HOSTNAME a4m2k +#else +#define CONFIG_HOSTNAME a3m071 +#endif + /* * Serial console configuration */ @@ -50,9 +57,6 @@
#define CONFIG_CMD_BSP #define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_REGINFO
@@ -61,7 +65,11 @@ */ #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* define for 66MHz speed - undef for 33MHz PCI clock speed */ +#ifdef CONFIG_A4M2K +#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 +#else #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 +#endif
/* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT @@ -76,33 +84,10 @@ #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
/* - * I2C configuration - */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* * NOR flash configuration */ #define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CONFIG_SYS_FLASH_SIZE 0x02000000 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 @@ -153,7 +138,11 @@ */ #define CONFIG_MPC5xxx_FEC #define CONFIG_MPC5xxx_FEC_MII100 +#ifdef CONFIG_A4M2K +#define CONFIG_PHY_ADDR 0x01 +#else #define CONFIG_PHY_ADDR 0x00 +#endif
/* * GPIO configuration @@ -166,19 +155,23 @@ * 2 means fpga ok */
+#ifdef CONFIG_A4M2K +#define CONFIG_SYS_GPS_PORT_CONFIG 0x0005C805 +#else /* for failsave-level 0 - full failsave */ #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005 /* for failsave-level 1 - only digiboard ok */ #define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C005 /* for failsave-level 2 - all ok */ #define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C005 +#endif
/* * Configuration matrix * MSB LSB - * failsave 0 0x1005C005 00010000000001011100000001100101 ( full failsave ) - * failsave 1 0x1005C005 00010000000001011100000001100101 ( digib.-ver ok ) - * failsave 2 0x1005C005 00010000000001011100000001100101 ( all ok ) + * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave ) + * failsave 1 0x1005C005 00010000000001011100000000000101 ( digib.-ver ok ) + * failsave 2 0x1005C005 00010000000001011100000000000101 ( all ok ) * || ||| || | ||| | | | | * || ||| || | ||| | | | | bit rev name * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1 @@ -254,30 +247,47 @@ #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE + +#ifdef CONFIG_A4M2K +/* external MRAM */ +#define CONFIG_SYS_CS1_START 0xf1000000 +#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */ +#endif + #define CONFIG_SYS_CS2_START 0xe0000000 #define CONFIG_SYS_CS2_SIZE 0x00100000
-/* FPGA slave io (512kiB) - see ticket #66 */ +/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */ #define CONFIG_SYS_CS3_START 0xE9000000 +#ifdef CONFIG_A4M2K +#define CONFIG_SYS_CS3_SIZE 0x00100000 +#else #define CONFIG_SYS_CS3_SIZE 0x00080000 +#endif /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ #define CONFIG_SYS_CS3_CFG 0x0032B900
+#ifndef CONFIG_A4M2K /* Diagnosis Interface - see ticket #63 */ #define CONFIG_SYS_CS4_START 0xEA000000 #define CONFIG_SYS_CS4_SIZE 0x00000001 /* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */ #define CONFIG_SYS_CS4_CFG 0x0002B900 +#endif
-/* FPGA master io (64kiB) - see ticket #66 */ +/* FPGA master io (64kiB / 1MiB) - see ticket #66 */ #define CONFIG_SYS_CS5_START 0xE8000000 +#ifdef CONFIG_A4M2K +#define CONFIG_SYS_CS5_SIZE 0x00100000 +#else #define CONFIG_SYS_CS5_SIZE 0x00010000 +#endif /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ #define CONFIG_SYS_CS5_CFG 0x0032B900
#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */ #define CONFIG_SYS_BOOTCS_CFG 0x0006F900 -#define CONFIG_SYS_CS1_CFG 0x0004FB00 +#define CONFIG_SYS_CS1_CFG 0x0008FD00 #define CONFIG_SYS_CS2_CFG 0x0006F90C #else /* for pci_clk = 33 MHz */ #define CONFIG_SYS_BOOTCS_CFG 0x0002F900 @@ -311,17 +321,25 @@ #define CONFIG_SYS_OS_BASE 0xfc080000 #define CONFIG_SYS_FDT_BASE 0xfc060000
-#define xstr(s) str(s) -#define str(s) #s - #define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ "netdev=eth0\0" \ "verify=no\0" \ + "loadaddr=200000\0" \ + "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \ + "kernel_addr_r=1000000\0" \ + "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \ + "fdt_addr_r=1800000\0" \ + "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ + "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \ + __stringify(CONFIG_HOSTNAME) ".dtb\0" \ + "rootpath=/opt/eldk-5.2.1/powerpc/" \ + "core-image-minimal-mtdutils-dropbear-generic\0" \ "consoledev=ttyPSC0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0"\ + "mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ @@ -332,18 +350,18 @@ "flash_mtd=run mtdargs addip addtty;" \ "bootm ${kernel_addr} - ${fdtaddr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \ - "net_nfs=sleep 2; tftp ${loadaddr} ${bootfile};" \ - "tftp c00000 ${fdtfile};" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ "run nfsargs addip addtty;" \ - "bootm ${loadaddr} - c00000\0" \ - "load=tftp ${loadaddr} u-boot.bin\0" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \ + "/u-boot-img.bin\0" \ "update=protect off fc000000 fc03ffff; " \ - "era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0"\ + "era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0" \ "upd=run load;run update\0" \ - "fdtaddr=" xstr(CONFIG_SYS_FDT_BASE) "\0" \ - "fdtfile=dtbFile\0" \ - "kernel_addr=" xstr(CONFIG_SYS_OS_BASE) "\0" \ + "bootdelay=3\0" \ + "bootcmd=run net_nfs\0" \ ""
#define CONFIG_BOOTCOMMAND "run flash_mtd"