Re: [PATCH V2] imx: Add support for i.MX8MN Beacon EmbeddedWorks devkit.

12 Jan 2021

On Fri, Dec 11, 2020 at 6:02 AM Adam Ford aford173@gmail.com wrote:
...
Beacon EmbeddedWorks is releasing a devkit based on the i.MX8M
Nano SoC consisting of baseboard + SOM.
The kit is based on the same design as the Beacon dev kit with
the i.MX8M Mini.
Signed-off-by: Adam Ford aford173@gmail.com
Gentle ping on this.  It's been over a month, and I was hoping to get
it integrated into the next release.
thanks
adam
...

V2:  Update README file to reference newer DDR firmware

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 02d04f5a8c..0ca895815c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -773,6 +773,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
        imx8mn-ddr4-evk.dtb \
        imx8mq-evk.dtb \
        imx8mm-beacon-kit.dtb \

  imx8mn-beacon-kit.dtb \
  imx8mq-phanbell.dtb \
  imx8mp-evk.dtb \
  imx8mq-pico-pi.dtb



diff --git a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
new file mode 100644
index 0000000000..49bff19a78
--- /dev/null
+++ b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*


Copyright 2020 Compass Electronics Group, LLC


*/


+/ {

  leds {


          compatible = "gpio-leds";



          led-0 {


                  label = "gen_led0";


                  gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;


                  default-state = "off";


          };



          led-1 {


                  label = "gen_led1";


                  gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;


                  default-state = "off";


          };



          led-2 {


                  label = "gen_led2";


                  gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;


                  default-state = "off";


          };



          led-3 {


                  pinctrl-names = "default";


                  pinctrl-0 = <&pinctrl_led3>;


                  label = "heartbeat";


                  gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;


                  linux,default-trigger = "heartbeat";


          };


  };



  reg_usdhc2_vmmc: regulator-usdhc2 {


          compatible = "regulator-fixed";


          regulator-name = "vsd_3v3";


          regulator-min-microvolt = <3300000>;


          regulator-max-microvolt = <3300000>;


          gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;


          enable-active-high;


  };



  reg_usb_otg_vbus: regulator-usb {


          compatible = "regulator-fixed";


          pinctrl-names = "default";


          pinctrl-0 = <&pinctrl_reg_usb_otg>;


          regulator-name = "usb_otg_vbus";


          regulator-min-microvolt = <5000000>;


          regulator-max-microvolt = <5000000>;


          gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;


          enable-active-high;


  };



+};



+&ecspi2 {

  pinctrl-names = "default";


  pinctrl-0 = <&pinctrl_espi2>;


  cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;


  status = "okay";



  eeprom@0 {


          compatible = "microchip,at25160bn", "atmel,at25";


          reg = <0>;


          spi-max-frequency = <5000000>;


          spi-cpha;


          spi-cpol;


          pagesize = <32>;


          size = <2048>;


          address-width = <16>;


  };



+};



+&i2c4 {

  clock-frequency = <400000>;


  pinctrl-names = "default";


  pinctrl-0 = <&pinctrl_i2c4>;


  status = "okay";



  pca6416_0: gpio@20 {


          compatible = "nxp,pcal6416";


          reg = <0x20>;


          pinctrl-names = "default";


          pinctrl-0 = <&pinctrl_pcal6414>;


          gpio-controller;


          #gpio-cells = <2>;


          interrupt-parent = <&gpio4>;


          interrupts = <27 IRQ_TYPE_LEVEL_LOW>;


  };



  pca6416_1: gpio@21 {


          compatible = "nxp,pcal6416";


          reg = <0x21>;


          gpio-controller;


          #gpio-cells = <2>;


          interrupt-parent = <&gpio4>;


          interrupts = <27 IRQ_TYPE_LEVEL_LOW>;


  };



+};



+&snvs_pwrkey {

  status = "okay";



+};



+&uart2 { /* console */

  pinctrl-names = "default";


  pinctrl-0 = <&pinctrl_uart2>;


  status = "okay";



+};



+&uart3 {

  pinctrl-names = "default";


  pinctrl-0 = <&pinctrl_uart3>;


  assigned-clocks = <&clk IMX8MN_CLK_UART3>;


  assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;


  status = "okay";



+};



+&usbotg1 {

  vbus-supply = <&reg_usb_otg_vbus>;


  disable-over-current;


  dr_mode="otg";


  status = "okay";



+};



+&usdhc2 {

  pinctrl-names = "default", "state_100mhz", "state_200mhz";


  pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;


  pinctrl-1 = <&pinctrl_usdhc2_100mhz>;


  pinctrl-2 = <&pinctrl_usdhc2_200mhz>;


  bus-width = <4>;


  vmmc-supply = <&reg_usdhc2_vmmc>;


  status = "okay";



+};



+&iomuxc {

  pinctrl_espi2: espi2grp {


          fsl,pins = <


                  MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK            0x82


                  MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI            0x82


                  MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO            0x82


                  MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9               0x41


          >;


  };



  pinctrl_i2c2: i2c2grp {


          fsl,pins = <


                  MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3


                  MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3


          >;


  };



  pinctrl_i2c4: i2c4grp {


          fsl,pins = <


                  MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL          0x400001c3


                  MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA          0x400001c3


          >;


  };



  pinctrl_led3: led3grp {


          fsl,pins = <


                  MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28       0x41


          >;


  };



  pinctrl_pcal6414: pcal6414-gpiogrp {


          fsl,pins = <


                  MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27               0x19


          >;


  };



  pinctrl_reg_usb_otg: reg-otggrp {


          fsl,pins = <


                  MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29     0x19


          >;


  };



  pinctrl_uart2: uart2grp {


          fsl,pins = <


                  MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140


                  MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140


          >;


  };



  pinctrl_uart3: uart3grp {


          fsl,pins = <


                  MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX   0x40


                  MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX   0x40


          >;


  };



  pinctrl_usdhc2_gpio: usdhc2gpiogrp {


          fsl,pins = <


                  MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B       0x41


                  MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41


          >;


  };



  pinctrl_usdhc2: usdhc2grp {


          fsl,pins = <


                  MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190


                  MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0


                  MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0


                  MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0


                  MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0


                  MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0


                  MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0


          >;


  };



  pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {


          fsl,pins = <


                  MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194


                  MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4


                  MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4


                  MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4


                  MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4


                  MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4


                  MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0


          >;


  };



  pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {


          fsl,pins = <


                  MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196


                  MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6


                  MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6


                  MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6


                  MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6


                  MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6


                  MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0


          >;


  };



+};
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
new file mode 100644
index 0000000000..bbc64a2819
--- /dev/null
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2020 Compass Electronics Group, LLC


*/


+/ {

  wdt-reboot {


          compatible = "wdt-reboot";


          wdt = <&wdog1>;


          u-boot,dm-spl;


  };



+};



+&{/soc@0} {

  u-boot,dm-pre-reloc;


  u-boot,dm-spl;



+};



+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {

  u-boot,dm-spl;



+};



+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {

  u-boot,dm-spl;



+};



+&aips1 {

  u-boot,dm-spl;


  u-boot,dm-pre-reloc;



+};



+&aips2 {

  u-boot,dm-spl;



+};



+&aips3 {

  u-boot,dm-spl;



+};



+&clk {

  u-boot,dm-spl;


  u-boot,dm-pre-reloc;



+};



+&gpio1 {

  u-boot,dm-spl;



+};



+&gpio2 {

  u-boot,dm-spl;



+};



+&i2c1 {

  u-boot,dm-spl;



+};



+&iomuxc {

  u-boot,dm-spl;



+};



+&osc_24m {

  u-boot,dm-spl;


  u-boot,dm-pre-reloc;



+};



+&pca6416_0 {

  compatible = "ti,tca6416";



+};



+&pca6416_1 {

  compatible = "ti,tca6416";



+};



+&pinctrl_i2c1 {

  u-boot,dm-spl;



+};



+&pinctrl_pmic {

  u-boot,dm-spl;



+};



+&pinctrl_uart2 {

  u-boot,dm-spl;



+};



+&pinctrl_usdhc2_gpio {

  u-boot,dm-spl;



+};



+&pinctrl_usdhc2 {

  u-boot,dm-spl;



+};



+&pinctrl_usdhc3 {

  u-boot,dm-spl;



+};



+&reg_usdhc2_vmmc {

  u-boot,off-on-delay-us = <20000>;



+};



+&usdhc1 {

  u-boot,dm-spl;


  sd-uhs-sdr104;


  sd-uhs-ddr50;



+};



+&usdhc2 {

  u-boot,dm-spl;


  sd-uhs-sdr104;


  sd-uhs-ddr50;



+};



+&usdhc3 {

  u-boot,dm-spl;


  mmc-hs400-1_8v;


  mmc-hs400-enhanced-strobe;



+};



+&wdog1 {

  u-boot,dm-spl;



+};
diff --git a/arch/arm/dts/imx8mn-beacon-kit.dts b/arch/arm/dts/imx8mn-beacon-kit.dts
new file mode 100644
index 0000000000..1392ce0258
--- /dev/null
+++ b/arch/arm/dts/imx8mn-beacon-kit.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*


Copyright 2020 Compass Electronics Group, LLC


*/


+/dts-v1/;



+#include "imx8mn.dtsi"
+#include "imx8mn-beacon-som.dtsi"
+#include "imx8mn-beacon-baseboard.dtsi"



+/ {

  model = "Beacon EmbeddedWorks i.MX8M Nano Development Kit";


  compatible = "beacon,imx8mn-beacon-kit", "fsl,imx8mn";



  chosen {


          stdout-path = &uart2;


  };



+};
diff --git a/arch/arm/dts/imx8mn-beacon-som.dtsi b/arch/arm/dts/imx8mn-beacon-som.dtsi
new file mode 100644
index 0000000000..52a50d97e0
--- /dev/null
+++ b/arch/arm/dts/imx8mn-beacon-som.dtsi
@@ -0,0 +1,405 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*


Copyright 2020 Compass Electronics Group, LLC


*/


+/ {

  usdhc1_pwrseq: usdhc1_pwrseq {


          compatible = "mmc-pwrseq-simple";


          pinctrl-names = "default";


          pinctrl-0 = <&pinctrl_usdhc1_gpio>;


          reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;


          clocks = <&osc_32k>;


          clock-names = "ext_clock";


          post-power-on-delay-ms = <80>;


  };



  memory@40000000 {


          device_type = "memory";


          reg = <0x0 0x40000000 0 0x80000000>;


  };



+};



+&A53_0 {

  cpu-supply = <&buck2_reg>;



+};



+&A53_1 {

  cpu-supply = <&buck2_reg>;



+};



+&A53_2 {

  cpu-supply = <&buck2_reg>;



+};



+&A53_3 {

  cpu-supply = <&buck2_reg>;



+};



+&fec1 {

  pinctrl-names = "default";


  pinctrl-0 = <&pinctrl_fec1>;


  phy-mode = "rgmii-id";


  phy-handle = <&ethphy0>;


  phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;


  fsl,magic-packet;


  status = "okay";



  mdio {


          #address-cells = <1>;


          #size-cells = <0>;



          ethphy0: ethernet-phy@0 {


                  compatible = "ethernet-phy-ieee802.3-c22";


                  reg = <0>;


          };


  };



+};



+&i2c1 {

  clock-frequency = <400000>;


  pinctrl-names = "default";


  pinctrl-0 = <&pinctrl_i2c1>;


  status = "okay";



  pmic@4b {


          compatible = "rohm,bd71847";


          reg = <0x4b>;


          pinctrl-names = "default";


          pinctrl-0 = <&pinctrl_pmic>;


          interrupt-parent = <&gpio1>;


          interrupts = <3 IRQ_TYPE_LEVEL_LOW>;


          rohm,reset-snvs-powered;



          regulators {


                  buck1_reg: BUCK1 {


                          regulator-name = "buck1";


                          regulator-min-microvolt = <700000>;


                          regulator-max-microvolt = <1300000>;


                          regulator-boot-on;


                          regulator-always-on;


                          regulator-ramp-delay = <1250>;


                  };



                  buck2_reg: BUCK2 {


                          regulator-name = "buck2";


                          regulator-min-microvolt = <700000>;


                          regulator-max-microvolt = <1300000>;


                          regulator-boot-on;


                          regulator-always-on;


                          regulator-ramp-delay = <1250>;


                          rohm,dvs-run-voltage = <1000000>;


                          rohm,dvs-idle-voltage = <900000>;


                  };



                  buck3_reg: BUCK3 {


                          // BUCK5 in datasheet


                          regulator-name = "buck3";


                          regulator-min-microvolt = <700000>;


                          regulator-max-microvolt = <1350000>;


                          regulator-boot-on;


                          regulator-always-on;


                  };



                  buck4_reg: BUCK4 {


                          // BUCK6 in datasheet


                          regulator-name = "buck4";


                          regulator-min-microvolt = <3000000>;


                          regulator-max-microvolt = <3300000>;


                          regulator-boot-on;


                          regulator-always-on;


                  };



                  buck5_reg: BUCK5 {


                          // BUCK7 in datasheet


                          regulator-name = "buck5";


                          regulator-min-microvolt = <1605000>;


                          regulator-max-microvolt = <1995000>;


                          regulator-boot-on;


                          regulator-always-on;


                  };



                  buck6_reg: BUCK6 {


                          // BUCK8 in datasheet


                          regulator-name = "buck6";


                          regulator-min-microvolt = <800000>;


                          regulator-max-microvolt = <1400000>;


                          regulator-boot-on;


                          regulator-always-on;


                  };



                  ldo1_reg: LDO1 {


                          regulator-name = "ldo1";


                          regulator-min-microvolt = <1600000>;


                          regulator-max-microvolt = <3300000>;


                          regulator-boot-on;


                          regulator-always-on;


                  };



                  ldo2_reg: LDO2 {


                          regulator-name = "ldo2";


                          regulator-min-microvolt = <800000>;


                          regulator-max-microvolt = <900000>;


                          regulator-boot-on;


                          regulator-always-on;


                  };



                  ldo3_reg: LDO3 {


                          regulator-name = "ldo3";


                          regulator-min-microvolt = <1800000>;


                          regulator-max-microvolt = <3300000>;


                          regulator-boot-on;


                          regulator-always-on;


                  };



                  ldo4_reg: LDO4 {


                          regulator-name = "ldo4";


                          regulator-min-microvolt = <900000>;


                          regulator-max-microvolt = <1800000>;


                          regulator-boot-on;


                          regulator-always-on;


                  };



                  ldo6_reg: LDO6 {


                          regulator-name = "ldo6";


                          regulator-min-microvolt = <900000>;


                          regulator-max-microvolt = <1800000>;


                          regulator-boot-on;


                          regulator-always-on;


                  };


          };


  };



+};



+&i2c3 {

  clock-frequency = <400000>;


  pinctrl-names = "default";


  pinctrl-0 = <&pinctrl_i2c3>;


  status = "okay";



  eeprom@50 {


          compatible = "microchip,24c64", "atmel,24c64";


          pagesize = <32>;


          read-only;      /* Manufacturing EEPROM programmed at factory */


          reg = <0x50>;


  };



  rtc@51 {


          compatible = "nxp,pcf85263";


          reg = <0x51>;


  };



+};



+&uart1 {

  pinctrl-names = "default";


  pinctrl-0 = <&pinctrl_uart1>;


  assigned-clocks = <&clk IMX8MN_CLK_UART1>;


  assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;


  uart-has-rtscts;


  status = "okay";



  bluetooth {


          compatible = "brcm,bcm43438-bt";


          shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;


          host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;


          device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;


          clocks = <&osc_32k>;


          max-speed = <4000000>;


          clock-names = "extclk";


  };



+};



+&usdhc1 {

  #address-cells = <1>;


  #size-cells = <0>;


  pinctrl-names = "default";


  pinctrl-0 = <&pinctrl_usdhc1>;


  bus-width = <4>;


  non-removable;


  cap-power-off-card;


  pm-ignore-notify;


  keep-power-in-suspend;


  mmc-pwrseq = <&usdhc1_pwrseq>;


  status = "okay";



  brcmf: bcrmf@1 {


          reg = <1>;


          compatible = "brcm,bcm4329-fmac";


          pinctrl-names = "default";


          pinctrl-0 = <&pinctrl_wlan>;


          interrupt-parent = <&gpio2>;


          interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;


          interrupt-names = "host-wake";


  };



+};



+&usdhc3 {

  pinctrl-names = "default", "state_100mhz", "state_200mhz";


  pinctrl-0 = <&pinctrl_usdhc3>;


  pinctrl-1 = <&pinctrl_usdhc3_100mhz>;


  pinctrl-2 = <&pinctrl_usdhc3_200mhz>;


  bus-width = <8>;


  non-removable;


  status = "okay";



+};



+&wdog1 {

  pinctrl-names = "default";


  pinctrl-0 = <&pinctrl_wdog>;


  fsl,ext-reset-output;


  status = "okay";



+};



+&iomuxc {

  pinctrl_fec1: fec1grp {


          fsl,pins = <


                  MX8MN_IOMUXC_ENET_MDC_ENET1_MDC         0x3


                  MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3


                  MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f


                  MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f


                  MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f


                  MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f


                  MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91


                  MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91


                  MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91


                  MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91


                  MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f


                  MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91


                  MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91


                  MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f


                  MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19


          >;


  };



  pinctrl_i2c1: i2c1grp {


          fsl,pins = <


                  MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3


                  MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3


          >;


  };



  pinctrl_i2c3: i2c3grp {


          fsl,pins = <


                  MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3


                  MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3


          >;


  };



  pinctrl_pmic: pmicirqgrp {


          fsl,pins = <


                  MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x141


          >;


  };



  pinctrl_uart1: uart1grp {


          fsl,pins = <


                  MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140


                  MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140


                  MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140


                  MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140


                  MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6        0x19


                  MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7        0x19


                  MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8        0x19


                  MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x141


          >;


  };



  pinctrl_usdhc1_gpio: usdhc1gpiogrp {


          fsl,pins = <


                  MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10     0x41


          >;


  };



  pinctrl_usdhc1: usdhc1grp {


          fsl,pins = <


                  MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x190


                  MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0


                  MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0


                  MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0


                  MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0


                  MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0


          >;


  };



  pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {


          fsl,pins = <


                  MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x194


                  MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4


                  MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4


                  MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4


                  MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4


                  MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4


          >;


  };



  pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {


          fsl,pins = <


                  MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x196


                  MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6


                  MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6


                  MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6


                  MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6


                  MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6


          >;


  };



  pinctrl_usdhc3: usdhc3grp {


          fsl,pins = <


                  MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190


                  MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0


                  MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0


                  MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0


                  MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0


                  MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0


                  MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0


                  MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0


                  MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0


                  MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0


                  MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190


          >;


  };



  pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {


          fsl,pins = <


                  MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194


                  MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4


                  MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4


                  MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4


                  MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4


                  MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4


                  MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4


                  MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4


                  MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4


                  MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4


                  MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194


          >;


  };



  pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {


          fsl,pins = <


                  MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196


                  MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6


                  MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6


                  MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6


                  MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6


                  MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6


                  MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6


                  MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6


                  MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6


                  MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6


                  MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196


          >;


  };



  pinctrl_wdog: wdoggrp {


          fsl,pins = <


                  MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6


          >;


  };



  pinctrl_wlan: wlangrp {


          fsl,pins = <


                  MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9                0x111


          >;


  };



+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 8615dc3bec..a84caeae7e 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -72,6 +72,12 @@ config TARGET_IMX8MM_BEACON
        select SUPPORT_SPL
        select IMX8M_LPDDR4
+config TARGET_IMX8MN_BEACON

  bool "imx8mn Beacon Embedded devkit"


  select IMX8MN


  select SUPPORT_SPL


  select IMX8M_LPDDR4




config TARGET_PHYCORE_IMX8MM
        bool "PHYTEC PHYCORE i.MX8MM"
        select IMX8MM
@@ -87,6 +93,7 @@ source "board/google/imx8mq_phanbell/Kconfig"
 source "board/technexion/pico-imx8mq/Kconfig"
 source "board/toradex/verdin-imx8mm/Kconfig"
 source "board/beacon/imx8mm/Kconfig"
+source "board/beacon/imx8mn/Kconfig"
 source "board/phytec/phycore_imx8mm/Kconfig"
endif
diff --git a/arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg b/arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg
new file mode 100644
index 0000000000..4c63b31db6
--- /dev/null
+++ b/arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*


Copyright 2019 NXP


*/


+#define __ASSEMBLY__



+FIT
+ROM_VERSION    v2
+BOOT_FROM      sd
+LOADER         spl/u-boot-spl-ddr.bin  0x912000
+SECOND_LOADER  u-boot.itb              0x40200000 0x60000



+DDR_FW lpddr4_pmu_train_1d_imem.bin
+DDR_FW lpddr4_pmu_train_1d_dmem.bin
+DDR_FW lpddr4_pmu_train_2d_imem.bin
+DDR_FW lpddr4_pmu_train_2d_dmem.bin
diff --git a/board/beacon/imx8mn/Kconfig b/board/beacon/imx8mn/Kconfig
new file mode 100644
index 0000000000..6ed17c00d8
--- /dev/null
+++ b/board/beacon/imx8mn/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_IMX8MN_BEACON



+config SYS_BOARD

  default "imx8mn"




+config SYS_VENDOR

  default "beacon"




+config SYS_CONFIG_NAME

  default "imx8mn_beacon"




+config IMX8MN_FORCE_NOM_SOC

  bool "Force to use nominal mode for SOC and ARM"


  default n




+source "board/freescale/common/Kconfig"



+endif
diff --git a/board/beacon/imx8mn/MAINTAINERS b/board/beacon/imx8mn/MAINTAINERS
new file mode 100644
index 0000000000..4e3fc713a0
--- /dev/null
+++ b/board/beacon/imx8mn/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8MN BEACON BOARD
+M:     Adam Ford aford173@gmail.com
+S:     Maintained
+F:     board/beacon/imx8mn/
+F:     include/configs/imx8mn_beacon.h
+F:     configs/imx8mn_beacon_defconfig
diff --git a/board/beacon/imx8mn/Makefile b/board/beacon/imx8mn/Makefile
new file mode 100644
index 0000000000..9e842de42f
--- /dev/null
+++ b/board/beacon/imx8mn/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2020 Compass Electronics Group, LLC
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#



+obj-y += imx8mn_beacon.o
+obj-y += ../../freescale/common/
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
+endif
diff --git a/board/beacon/imx8mn/README b/board/beacon/imx8mn/README
new file mode 100644
index 0000000000..d3c90d31dd
--- /dev/null
+++ b/board/beacon/imx8mn/README
@@ -0,0 +1,39 @@
+U-Boot for the Beacon EmbeddedWorks i.MX8M Nano Devkit



+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Boot



+Get and Build the ARM Trusted firmware
+======================================
+Note: $(srctree) is U-Boot source directory



+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ git checkout imx_5.4.47_2.2.0
+$ make PLAT=imx8mn bl31 CROSS_COMPILE=aarch64-linux-gnu-
+$ cp build/imx8mm/release/bl31.bin $(srctree)



+Get the DDR firmware
+====================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+$ chmod +x firmware-imx-8.9.bin
+$ ./firmware-imx-8.9
+$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)



+Build U-Boot
+============
+$ make imx8mn_beacon_defconfig
+$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x960000



+Burn U-Boot to microSD Card
+===========================
+$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32



+Boot
+====
+Set baseboard DIP switch:
+S17: 1100XXXX



diff --git a/board/beacon/imx8mn/imx8mn_beacon.c b/board/beacon/imx8mn/imx8mn_beacon.c
new file mode 100644
index 0000000000..51deb7b4e6
--- /dev/null
+++ b/board/beacon/imx8mn/imx8mn_beacon.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2020 Compass Electronics Group, LLC


*/


+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>



+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>



+DECLARE_GLOBAL_DATA_PTR;



+#if IS_ENABLED(CONFIG_FEC_MXC)
+static int setup_fec(void)
+{

  struct iomuxc_gpr_base_regs *gpr =


          (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;



  /* Use 125M anatop REF_CLK1 for ENET1, not from external */


  clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);



  return 0;



+}



+int board_phy_config(struct phy_device *phydev)
+{

  /* enable rgmii rxc skew and phy mode select to RGMII copper */


  phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);


  phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);



  phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);


  phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);


  phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);


  phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);



  if (phydev->drv->config)


          phydev->drv->config(phydev);


  return 0;



+}
+#endif



+int board_init(void)
+{

  if (IS_ENABLED(CONFIG_FEC_MXC))


          setup_fec();



  return 0;



+}



+int board_mmc_get_env_dev(int devno)
+{

  return CONFIG_SYS_MMC_ENV_DEV;



+}
diff --git a/board/beacon/imx8mn/lpddr4_timing.c b/board/beacon/imx8mn/lpddr4_timing.c
new file mode 100644
index 0000000000..3c1ad392f1
--- /dev/null
+++ b/board/beacon/imx8mn/lpddr4_timing.c
@@ -0,0 +1,1434 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2020 Compass Electronics Group, LLC


*/


+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>



+struct dram_cfg_param ddr_ddrc_cfg[] = {

  /** Initialize DDRC registers **/


  { 0x3d400304, 0x1 },


  { 0x3d400030, 0x1 },


  { 0x3d400000, 0xa1080020 },


  { 0x3d400020, 0x202 },


  { 0x3d400024, 0x3e800 },


  { 0x3d400064, 0x3000e0 },


  { 0x3d4000d0, 0xc003061c },


  { 0x3d4000d4, 0x9e0000 },


  { 0x3d4000dc, 0xd4002d },


  { 0x3d4000e0, 0x310000 },


  { 0x3d4000e8, 0x66004d },


  { 0x3d4000ec, 0x16004d },


  { 0x3d400100, 0x1a200d22 },


  { 0x3d400104, 0x60633 },


  { 0x3d40010c, 0xc0c000 },


  { 0x3d400110, 0xf04080f },


  { 0x3d400114, 0x2040c0c },


  { 0x3d400118, 0x1010007 },


  { 0x3d40011c, 0x401 },


  { 0x3d400130, 0x20600 },


  { 0x3d400134, 0xc100002 },


  { 0x3d400138, 0xe6 },


  { 0x3d400144, 0xa00050 },


  { 0x3d400180, 0x3200018 },


  { 0x3d400184, 0x28061a8 },


  { 0x3d400188, 0x0 },


  { 0x3d400190, 0x497820a },


  { 0x3d400194, 0x80303 },


  { 0x3d4001b4, 0x170a },


  { 0x3d4001a0, 0xe0400018 },


  { 0x3d4001a4, 0xdf00e4 },


  { 0x3d4001a8, 0x80000000 },


  { 0x3d4001b0, 0x11 },


  { 0x3d4001c0, 0x1 },


  { 0x3d4001c4, 0x1 },


  { 0x3d4000f4, 0xc99 },


  { 0x3d400108, 0x70e1617 },


  { 0x3d400200, 0x1f },


  { 0x3d40020c, 0x0 },


  { 0x3d400210, 0x1f1f },


  { 0x3d400204, 0x80808 },


  { 0x3d400214, 0x7070707 },


  { 0x3d400218, 0x7070707 },


  { 0x3d400250, 0x29001701 },


  { 0x3d400254, 0x2c },


  { 0x3d40025c, 0x4000030 },


  { 0x3d400264, 0x900093e7 },


  { 0x3d40026c, 0x2005574 },


  { 0x3d400400, 0x111 },


  { 0x3d400408, 0x72ff },


  { 0x3d400494, 0x2100e07 },


  { 0x3d400498, 0x620096 },


  { 0x3d40049c, 0x1100e07 },


  { 0x3d4004a0, 0xc8012c },


  { 0x3d402020, 0x0 },


  { 0x3d402024, 0x7d00 },


  { 0x3d402050, 0x20d040 },


  { 0x3d402064, 0x6001c },


  { 0x3d4020dc, 0x840000 },


  { 0x3d4020e0, 0x310000 },


  { 0x3d4020e8, 0x66004d },


  { 0x3d4020ec, 0x16004d },


  { 0x3d402100, 0xa040105 },


  { 0x3d402104, 0x30407 },


  { 0x3d402108, 0x203060b },


  { 0x3d40210c, 0x505000 },


  { 0x3d402110, 0x2040202 },


  { 0x3d402114, 0x2030202 },


  { 0x3d402118, 0x1010004 },


  { 0x3d40211c, 0x301 },


  { 0x3d402130, 0x20300 },


  { 0x3d402134, 0xa100002 },


  { 0x3d402138, 0x1d },


  { 0x3d402144, 0x14000a },


  { 0x3d402180, 0x640004 },


  { 0x3d402190, 0x3818200 },


  { 0x3d402194, 0x80303 },


  { 0x3d4021b4, 0x100 },


  { 0x3d4020f4, 0xc99 },


  { 0x3d403020, 0x0 },


  { 0x3d403024, 0x1f40 },


  { 0x3d403050, 0x20d040 },


  { 0x3d403064, 0x30007 },


  { 0x3d4030dc, 0x840000 },


  { 0x3d4030e0, 0x310000 },


  { 0x3d4030e8, 0x66004d },


  { 0x3d4030ec, 0x16004d },


  { 0x3d403100, 0xa010102 },


  { 0x3d403104, 0x30404 },


  { 0x3d403108, 0x203060b },


  { 0x3d40310c, 0x505000 },


  { 0x3d403110, 0x2040202 },


  { 0x3d403114, 0x2030202 },


  { 0x3d403118, 0x1010004 },


  { 0x3d40311c, 0x301 },


  { 0x3d403130, 0x20300 },


  { 0x3d403134, 0xa100002 },


  { 0x3d403138, 0x8 },


  { 0x3d403144, 0x50003 },


  { 0x3d403180, 0x190004 },


  { 0x3d403190, 0x3818200 },


  { 0x3d403194, 0x80303 },


  { 0x3d4031b4, 0x100 },


  { 0x3d4030f4, 0xc99 },


  { 0x3d400028, 0x0 },



+};



+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {

  { 0x100a0, 0x0 },


  { 0x100a1, 0x1 },


  { 0x100a2, 0x3 },


  { 0x100a3, 0x2 },


  { 0x100a4, 0x4 },


  { 0x100a5, 0x5 },


  { 0x100a6, 0x7 },


  { 0x100a7, 0x6 },


  { 0x110a0, 0x0 },


  { 0x110a1, 0x1 },


  { 0x110a2, 0x2 },


  { 0x110a3, 0x3 },


  { 0x110a4, 0x5 },


  { 0x110a5, 0x4 },


  { 0x110a6, 0x6 },


  { 0x110a7, 0x7 },


  { 0x1005f, 0x1ff },


  { 0x1015f, 0x1ff },


  { 0x1105f, 0x1ff },


  { 0x1115f, 0x1ff },


  { 0x11005f, 0x1ff },


  { 0x11015f, 0x1ff },


  { 0x11105f, 0x1ff },


  { 0x11115f, 0x1ff },


  { 0x21005f, 0x1ff },


  { 0x21015f, 0x1ff },


  { 0x21105f, 0x1ff },


  { 0x21115f, 0x1ff },


  { 0x55, 0x1ff },


  { 0x1055, 0x1ff },


  { 0x2055, 0x1ff },


  { 0x3055, 0x1ff },


  { 0x4055, 0x1ff },


  { 0x5055, 0x1ff },


  { 0x6055, 0x1ff },


  { 0x7055, 0x1ff },


  { 0x8055, 0x1ff },


  { 0x9055, 0x1ff },


  { 0x200c5, 0x19 },


  { 0x1200c5, 0x7 },


  { 0x2200c5, 0x7 },


  { 0x2002e, 0x2 },


  { 0x12002e, 0x2 },


  { 0x22002e, 0x2 },


  { 0x90204, 0x0 },


  { 0x190204, 0x0 },


  { 0x290204, 0x0 },


  { 0x20024, 0x1a3 },


  { 0x2003a, 0x2 },


  { 0x120024, 0x1a3 },


  { 0x2003a, 0x2 },


  { 0x220024, 0x1a3 },


  { 0x2003a, 0x2 },


  { 0x20056, 0x3 },


  { 0x120056, 0x3 },


  { 0x220056, 0x3 },


  { 0x1004d, 0xe00 },


  { 0x1014d, 0xe00 },


  { 0x1104d, 0xe00 },


  { 0x1114d, 0xe00 },


  { 0x11004d, 0xe00 },


  { 0x11014d, 0xe00 },


  { 0x11104d, 0xe00 },


  { 0x11114d, 0xe00 },


  { 0x21004d, 0xe00 },


  { 0x21014d, 0xe00 },


  { 0x21104d, 0xe00 },


  { 0x21114d, 0xe00 },


  { 0x10049, 0xeba },


  { 0x10149, 0xeba },


  { 0x11049, 0xeba },


  { 0x11149, 0xeba },


  { 0x110049, 0xeba },


  { 0x110149, 0xeba },


  { 0x111049, 0xeba },


  { 0x111149, 0xeba },


  { 0x210049, 0xeba },


  { 0x210149, 0xeba },


  { 0x211049, 0xeba },


  { 0x211149, 0xeba },


  { 0x43, 0x63 },


  { 0x1043, 0x63 },


  { 0x2043, 0x63 },


  { 0x3043, 0x63 },


  { 0x4043, 0x63 },


  { 0x5043, 0x63 },


  { 0x6043, 0x63 },


  { 0x7043, 0x63 },


  { 0x8043, 0x63 },


  { 0x9043, 0x63 },


  { 0x20018, 0x1 },


  { 0x20075, 0x4 },


  { 0x20050, 0x0 },


  { 0x20008, 0x320 },


  { 0x120008, 0x64 },


  { 0x220008, 0x19 },


  { 0x20088, 0x9 },


  { 0x200b2, 0xdc },


  { 0x10043, 0x5a1 },


  { 0x10143, 0x5a1 },


  { 0x11043, 0x5a1 },


  { 0x11143, 0x5a1 },


  { 0x1200b2, 0xdc },


  { 0x110043, 0x5a1 },


  { 0x110143, 0x5a1 },


  { 0x111043, 0x5a1 },


  { 0x111143, 0x5a1 },


  { 0x2200b2, 0xdc },


  { 0x210043, 0x5a1 },


  { 0x210143, 0x5a1 },


  { 0x211043, 0x5a1 },


  { 0x211143, 0x5a1 },


  { 0x200fa, 0x1 },


  { 0x1200fa, 0x1 },


  { 0x2200fa, 0x1 },


  { 0x20019, 0x1 },


  { 0x120019, 0x1 },


  { 0x220019, 0x1 },


  { 0x200f0, 0x660 },


  { 0x200f1, 0x0 },


  { 0x200f2, 0x4444 },


  { 0x200f3, 0x8888 },


  { 0x200f4, 0x5665 },


  { 0x200f5, 0x0 },


  { 0x200f6, 0x0 },


  { 0x200f7, 0xf000 },


  { 0x20025, 0x0 },


  { 0x2002d, 0x0 },


  { 0x12002d, 0x0 },


  { 0x22002d, 0x0 },


  { 0x2005b, 0x7529 },


  { 0x2005c, 0x0 },


  { 0x200c7, 0x21 },


  { 0x200ca, 0x24 },


  { 0x200cc, 0x1f7 },


  { 0x1200c7, 0x21 },


  { 0x1200ca, 0x24 },


  { 0x1200cc, 0x1f7 },


  { 0x2200c7, 0x21 },


  { 0x2200ca, 0x24 },


  { 0x2200cc, 0x1f7 },


  { 0x2007d, 0x212 },


  { 0x12007d, 0x212 },


  { 0x22007d, 0x212 },


  { 0x2007c, 0x61 },


  { 0x12007c, 0x61 },


  { 0x22007c, 0x61 },


  { 0x1004a, 0x500 },


  { 0x1104a, 0x500 },


  { 0x2002c, 0x0 },



+};



+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {

  {0x0200b2, 0x0},


  {0x1200b2, 0x0},


  {0x2200b2, 0x0},


  {0x0200cb, 0x0},


  {0x010043, 0x0},


  {0x110043, 0x0},


  {0x210043, 0x0},


  {0x010143, 0x0},


  {0x110143, 0x0},


  {0x210143, 0x0},


  {0x011043, 0x0},


  {0x111043, 0x0},


  {0x211043, 0x0},


  {0x011143, 0x0},


  {0x111143, 0x0},


  {0x211143, 0x0},


  {0x000080, 0x0},


  {0x100080, 0x0},


  {0x200080, 0x0},


  {0x001080, 0x0},


  {0x101080, 0x0},


  {0x201080, 0x0},


  {0x002080, 0x0},


  {0x102080, 0x0},


  {0x202080, 0x0},


  {0x003080, 0x0},


  {0x103080, 0x0},


  {0x203080, 0x0},


  {0x004080, 0x0},


  {0x104080, 0x0},


  {0x204080, 0x0},


  {0x005080, 0x0},


  {0x105080, 0x0},


  {0x205080, 0x0},


  {0x006080, 0x0},


  {0x106080, 0x0},


  {0x206080, 0x0},


  {0x007080, 0x0},


  {0x107080, 0x0},


  {0x207080, 0x0},


  {0x008080, 0x0},


  {0x108080, 0x0},


  {0x208080, 0x0},


  {0x009080, 0x0},


  {0x109080, 0x0},


  {0x209080, 0x0},


  {0x010080, 0x0},


  {0x110080, 0x0},


  {0x210080, 0x0},


  {0x010180, 0x0},


  {0x110180, 0x0},


  {0x210180, 0x0},


  {0x011080, 0x0},


  {0x111080, 0x0},


  {0x211080, 0x0},


  {0x011180, 0x0},


  {0x111180, 0x0},


  {0x211180, 0x0},


  {0x010081, 0x0},


  {0x110081, 0x0},


  {0x210081, 0x0},


  {0x010181, 0x0},


  {0x110181, 0x0},


  {0x210181, 0x0},


  {0x011081, 0x0},


  {0x111081, 0x0},


  {0x211081, 0x0},


  {0x011181, 0x0},


  {0x111181, 0x0},


  {0x211181, 0x0},


  {0x0100d0, 0x0},


  {0x1100d0, 0x0},


  {0x2100d0, 0x0},


  {0x0101d0, 0x0},


  {0x1101d0, 0x0},


  {0x2101d0, 0x0},


  {0x0110d0, 0x0},


  {0x1110d0, 0x0},


  {0x2110d0, 0x0},


  {0x0111d0, 0x0},


  {0x1111d0, 0x0},


  {0x2111d0, 0x0},


  {0x0100d1, 0x0},


  {0x1100d1, 0x0},


  {0x2100d1, 0x0},


  {0x0101d1, 0x0},


  {0x1101d1, 0x0},


  {0x2101d1, 0x0},


  {0x0110d1, 0x0},


  {0x1110d1, 0x0},


  {0x2110d1, 0x0},


  {0x0111d1, 0x0},


  {0x1111d1, 0x0},


  {0x2111d1, 0x0},


  {0x010068, 0x0},


  {0x010168, 0x0},


  {0x010268, 0x0},


  {0x010368, 0x0},


  {0x010468, 0x0},


  {0x010568, 0x0},


  {0x010668, 0x0},


  {0x010768, 0x0},


  {0x010868, 0x0},


  {0x011068, 0x0},


  {0x011168, 0x0},


  {0x011268, 0x0},


  {0x011368, 0x0},


  {0x011468, 0x0},


  {0x011568, 0x0},


  {0x011668, 0x0},


  {0x011768, 0x0},


  {0x011868, 0x0},


  {0x010069, 0x0},


  {0x010169, 0x0},


  {0x010269, 0x0},


  {0x010369, 0x0},


  {0x010469, 0x0},


  {0x010569, 0x0},


  {0x010669, 0x0},


  {0x010769, 0x0},


  {0x010869, 0x0},


  {0x011069, 0x0},


  {0x011169, 0x0},


  {0x011269, 0x0},


  {0x011369, 0x0},


  {0x011469, 0x0},


  {0x011569, 0x0},


  {0x011669, 0x0},


  {0x011769, 0x0},


  {0x011869, 0x0},


  {0x01008c, 0x0},


  {0x11008c, 0x0},


  {0x21008c, 0x0},


  {0x01018c, 0x0},


  {0x11018c, 0x0},


  {0x21018c, 0x0},


  {0x01108c, 0x0},


  {0x11108c, 0x0},


  {0x21108c, 0x0},


  {0x01118c, 0x0},


  {0x11118c, 0x0},


  {0x21118c, 0x0},


  {0x01008d, 0x0},


  {0x11008d, 0x0},


  {0x21008d, 0x0},


  {0x01018d, 0x0},


  {0x11018d, 0x0},


  {0x21018d, 0x0},


  {0x01108d, 0x0},


  {0x11108d, 0x0},


  {0x21108d, 0x0},


  {0x01118d, 0x0},


  {0x11118d, 0x0},


  {0x21118d, 0x0},


  {0x0100c0, 0x0},


  {0x1100c0, 0x0},


  {0x2100c0, 0x0},


  {0x0101c0, 0x0},


  {0x1101c0, 0x0},


  {0x2101c0, 0x0},


  {0x0102c0, 0x0},


  {0x1102c0, 0x0},


  {0x2102c0, 0x0},


  {0x0103c0, 0x0},


  {0x1103c0, 0x0},


  {0x2103c0, 0x0},


  {0x0104c0, 0x0},


  {0x1104c0, 0x0},


  {0x2104c0, 0x0},


  {0x0105c0, 0x0},


  {0x1105c0, 0x0},


  {0x2105c0, 0x0},


  {0x0106c0, 0x0},


  {0x1106c0, 0x0},


  {0x2106c0, 0x0},


  {0x0107c0, 0x0},


  {0x1107c0, 0x0},


  {0x2107c0, 0x0},


  {0x0108c0, 0x0},


  {0x1108c0, 0x0},


  {0x2108c0, 0x0},


  {0x0110c0, 0x0},


  {0x1110c0, 0x0},


  {0x2110c0, 0x0},


  {0x0111c0, 0x0},


  {0x1111c0, 0x0},


  {0x2111c0, 0x0},


  {0x0112c0, 0x0},


  {0x1112c0, 0x0},


  {0x2112c0, 0x0},


  {0x0113c0, 0x0},


  {0x1113c0, 0x0},


  {0x2113c0, 0x0},


  {0x0114c0, 0x0},


  {0x1114c0, 0x0},


  {0x2114c0, 0x0},


  {0x0115c0, 0x0},


  {0x1115c0, 0x0},


  {0x2115c0, 0x0},


  {0x0116c0, 0x0},


  {0x1116c0, 0x0},


  {0x2116c0, 0x0},


  {0x0117c0, 0x0},


  {0x1117c0, 0x0},


  {0x2117c0, 0x0},


  {0x0118c0, 0x0},


  {0x1118c0, 0x0},


  {0x2118c0, 0x0},


  {0x0100c1, 0x0},


  {0x1100c1, 0x0},


  {0x2100c1, 0x0},


  {0x0101c1, 0x0},


  {0x1101c1, 0x0},


  {0x2101c1, 0x0},


  {0x0102c1, 0x0},


  {0x1102c1, 0x0},


  {0x2102c1, 0x0},


  {0x0103c1, 0x0},


  {0x1103c1, 0x0},


  {0x2103c1, 0x0},


  {0x0104c1, 0x0},


  {0x1104c1, 0x0},


  {0x2104c1, 0x0},


  {0x0105c1, 0x0},


  {0x1105c1, 0x0},


  {0x2105c1, 0x0},


  {0x0106c1, 0x0},


  {0x1106c1, 0x0},


  {0x2106c1, 0x0},


  {0x0107c1, 0x0},


  {0x1107c1, 0x0},


  {0x2107c1, 0x0},


  {0x0108c1, 0x0},


  {0x1108c1, 0x0},


  {0x2108c1, 0x0},


  {0x0110c1, 0x0},


  {0x1110c1, 0x0},


  {0x2110c1, 0x0},


  {0x0111c1, 0x0},


  {0x1111c1, 0x0},


  {0x2111c1, 0x0},


  {0x0112c1, 0x0},


  {0x1112c1, 0x0},


  {0x2112c1, 0x0},


  {0x0113c1, 0x0},


  {0x1113c1, 0x0},


  {0x2113c1, 0x0},


  {0x0114c1, 0x0},


  {0x1114c1, 0x0},


  {0x2114c1, 0x0},


  {0x0115c1, 0x0},


  {0x1115c1, 0x0},


  {0x2115c1, 0x0},


  {0x0116c1, 0x0},


  {0x1116c1, 0x0},


  {0x2116c1, 0x0},


  {0x0117c1, 0x0},


  {0x1117c1, 0x0},


  {0x2117c1, 0x0},


  {0x0118c1, 0x0},


  {0x1118c1, 0x0},


  {0x2118c1, 0x0},


  {0x010020, 0x0},


  {0x110020, 0x0},


  {0x210020, 0x0},


  {0x011020, 0x0},


  {0x111020, 0x0},


  {0x211020, 0x0},


  {0x020072, 0x0},


  {0x020073, 0x0},


  {0x020074, 0x0},


  {0x0100aa, 0x0},


  {0x0110aa, 0x0},


  {0x020010, 0x0},


  {0x120010, 0x0},


  {0x220010, 0x0},


  {0x020011, 0x0},


  {0x120011, 0x0},


  {0x220011, 0x0},


  {0x0100ae, 0x0},


  {0x1100ae, 0x0},


  {0x2100ae, 0x0},


  {0x0100af, 0x0},


  {0x1100af, 0x0},


  {0x2100af, 0x0},


  {0x0110ae, 0x0},


  {0x1110ae, 0x0},


  {0x2110ae, 0x0},


  {0x0110af, 0x0},


  {0x1110af, 0x0},


  {0x2110af, 0x0},


  {0x020020, 0x0},


  {0x120020, 0x0},


  {0x220020, 0x0},


  {0x0100a0, 0x0},


  {0x0100a1, 0x0},


  {0x0100a2, 0x0},


  {0x0100a3, 0x0},


  {0x0100a4, 0x0},


  {0x0100a5, 0x0},


  {0x0100a6, 0x0},


  {0x0100a7, 0x0},


  {0x0110a0, 0x0},


  {0x0110a1, 0x0},


  {0x0110a2, 0x0},


  {0x0110a3, 0x0},


  {0x0110a4, 0x0},


  {0x0110a5, 0x0},


  {0x0110a6, 0x0},


  {0x0110a7, 0x0},


  {0x02007c, 0x0},


  {0x12007c, 0x0},


  {0x22007c, 0x0},


  {0x02007d, 0x0},


  {0x12007d, 0x0},


  {0x22007d, 0x0},


  {0x0400fd, 0x0},


  {0x0400c0, 0x0},


  {0x090201, 0x0},


  {0x190201, 0x0},


  {0x290201, 0x0},


  {0x090202, 0x0},


  {0x190202, 0x0},


  {0x290202, 0x0},


  {0x090203, 0x0},


  {0x190203, 0x0},


  {0x290203, 0x0},


  {0x090204, 0x0},


  {0x190204, 0x0},


  {0x290204, 0x0},


  {0x090205, 0x0},


  {0x190205, 0x0},


  {0x290205, 0x0},


  {0x090206, 0x0},


  {0x190206, 0x0},


  {0x290206, 0x0},


  {0x090207, 0x0},


  {0x190207, 0x0},


  {0x290207, 0x0},


  {0x090208, 0x0},


  {0x190208, 0x0},


  {0x290208, 0x0},


  {0x010062, 0x0},


  {0x010162, 0x0},


  {0x010262, 0x0},


  {0x010362, 0x0},


  {0x010462, 0x0},


  {0x010562, 0x0},


  {0x010662, 0x0},


  {0x010762, 0x0},


  {0x010862, 0x0},


  {0x011062, 0x0},


  {0x011162, 0x0},


  {0x011262, 0x0},


  {0x011362, 0x0},


  {0x011462, 0x0},


  {0x011562, 0x0},


  {0x011662, 0x0},


  {0x011762, 0x0},


  {0x011862, 0x0},


  {0x020077, 0x0},


  {0x010001, 0x0},


  {0x011001, 0x0},


  {0x010040, 0x0},


  {0x010140, 0x0},


  {0x010240, 0x0},


  {0x010340, 0x0},


  {0x010440, 0x0},


  {0x010540, 0x0},


  {0x010640, 0x0},


  {0x010740, 0x0},


  {0x010840, 0x0},


  {0x010030, 0x0},


  {0x010130, 0x0},


  {0x010230, 0x0},


  {0x010330, 0x0},


  {0x010430, 0x0},


  {0x010530, 0x0},


  {0x010630, 0x0},


  {0x010730, 0x0},


  {0x010830, 0x0},


  {0x011040, 0x0},


  {0x011140, 0x0},


  {0x011240, 0x0},


  {0x011340, 0x0},


  {0x011440, 0x0},


  {0x011540, 0x0},


  {0x011640, 0x0},


  {0x011740, 0x0},


  {0x011840, 0x0},


  {0x011030, 0x0},


  {0x011130, 0x0},


  {0x011230, 0x0},


  {0x011330, 0x0},


  {0x011430, 0x0},


  {0x011530, 0x0},


  {0x011630, 0x0},


  {0x011730, 0x0},


  {0x011830, 0x0},



+};



+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {

  { 0xd0000, 0x0 },


  { 0x54003, 0xc80 },


  { 0x54004, 0x2 },


  { 0x54005, 0x2228 },


  { 0x54006, 0x11 },


  { 0x54008, 0x131f },


  { 0x54009, 0xc8 },


  { 0x5400b, 0x2 },


  { 0x5400f, 0x100 },


  { 0x54012, 0x110 },


  { 0x54019, 0x2dd4 },


  { 0x5401a, 0x31 },


  { 0x5401b, 0x4d66 },


  { 0x5401c, 0x4d00 },


  { 0x5401e, 0x16 },


  { 0x5401f, 0x2dd4 },


  { 0x54020, 0x31 },


  { 0x54021, 0x4d66 },


  { 0x54022, 0x4d00 },


  { 0x54024, 0x16 },


  { 0x54032, 0xd400 },


  { 0x54033, 0x312d },


  { 0x54034, 0x6600 },


  { 0x54035, 0x4d },


  { 0x54036, 0x4d },


  { 0x54037, 0x1600 },


  { 0x54038, 0xd400 },


  { 0x54039, 0x312d },


  { 0x5403a, 0x6600 },


  { 0x5403b, 0x4d },


  { 0x5403c, 0x4d },


  { 0x5403d, 0x1600 },


  { 0xd0000, 0x1 },



+};



+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {

  { 0xd0000, 0x0 },


  { 0x54002, 0x101 },


  { 0x54003, 0x190 },


  { 0x54004, 0x2 },


  { 0x54005, 0x2228 },


  { 0x54006, 0x11 },


  { 0x54008, 0x121f },


  { 0x54009, 0xc8 },


  { 0x5400b, 0x2 },


  { 0x5400f, 0x100 },


  { 0x54012, 0x110 },


  { 0x54019, 0x84 },


  { 0x5401a, 0x31 },


  { 0x5401b, 0x4d66 },


  { 0x5401c, 0x4d00 },


  { 0x5401e, 0x16 },


  { 0x5401f, 0x84 },


  { 0x54020, 0x31 },


  { 0x54021, 0x4d66 },


  { 0x54022, 0x4d00 },


  { 0x54024, 0x16 },


  { 0x54032, 0x8400 },


  { 0x54033, 0x3100 },


  { 0x54034, 0x6600 },


  { 0x54035, 0x4d },


  { 0x54036, 0x4d },


  { 0x54037, 0x1600 },


  { 0x54038, 0x8400 },


  { 0x54039, 0x3100 },


  { 0x5403a, 0x6600 },


  { 0x5403b, 0x4d },


  { 0x5403c, 0x4d },


  { 0x5403d, 0x1600 },


  { 0xd0000, 0x1 },



+};



+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {

  { 0xd0000, 0x0 },


  { 0x54002, 0x102 },


  { 0x54003, 0x64 },


  { 0x54004, 0x2 },


  { 0x54005, 0x2228 },


  { 0x54006, 0x11 },


  { 0x54008, 0x121f },


  { 0x54009, 0xc8 },


  { 0x5400b, 0x2 },


  { 0x5400f, 0x100 },


  { 0x54012, 0x110 },


  { 0x54019, 0x84 },


  { 0x5401a, 0x31 },


  { 0x5401b, 0x4d66 },


  { 0x5401c, 0x4d00 },


  { 0x5401e, 0x16 },


  { 0x5401f, 0x84 },


  { 0x54020, 0x31 },


  { 0x54021, 0x4d66 },


  { 0x54022, 0x4d00 },


  { 0x54024, 0x16 },


  { 0x54032, 0x8400 },


  { 0x54033, 0x3100 },


  { 0x54034, 0x6600 },


  { 0x54035, 0x4d },


  { 0x54036, 0x4d },


  { 0x54037, 0x1600 },


  { 0x54038, 0x8400 },


  { 0x54039, 0x3100 },


  { 0x5403a, 0x6600 },


  { 0x5403b, 0x4d },


  { 0x5403c, 0x4d },


  { 0x5403d, 0x1600 },


  { 0xd0000, 0x1 },



+};



+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {

  { 0xd0000, 0x0 },


  { 0x54003, 0xc80 },


  { 0x54004, 0x2 },


  { 0x54005, 0x2228 },


  { 0x54006, 0x11 },


  { 0x54008, 0x61 },


  { 0x54009, 0xc8 },


  { 0x5400b, 0x2 },


  { 0x5400d, 0x100 },


  { 0x5400f, 0x100 },


  { 0x54010, 0x1f7f },


  { 0x54012, 0x110 },


  { 0x54019, 0x2dd4 },


  { 0x5401a, 0x31 },


  { 0x5401b, 0x4d66 },


  { 0x5401c, 0x4d00 },


  { 0x5401e, 0x16 },


  { 0x5401f, 0x2dd4 },


  { 0x54020, 0x31 },


  { 0x54021, 0x4d66 },


  { 0x54022, 0x4d00 },


  { 0x54024, 0x16 },


  { 0x54032, 0xd400 },


  { 0x54033, 0x312d },


  { 0x54034, 0x6600 },


  { 0x54035, 0x4d },


  { 0x54036, 0x4d },


  { 0x54037, 0x1600 },


  { 0x54038, 0xd400 },


  { 0x54039, 0x312d },


  { 0x5403a, 0x6600 },


  { 0x5403b, 0x4d },


  { 0x5403c, 0x4d },


  { 0x5403d, 0x1600 },


  { 0xd0000, 0x1 },



+};



+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {

  { 0xd0000, 0x0 },


  { 0x90000, 0x10 },


  { 0x90001, 0x400 },


  { 0x90002, 0x10e },


  { 0x90003, 0x0 },


  { 0x90004, 0x0 },


  { 0x90005, 0x8 },


  { 0x90029, 0xb },


  { 0x9002a, 0x480 },


  { 0x9002b, 0x109 },


  { 0x9002c, 0x8 },


  { 0x9002d, 0x448 },


  { 0x9002e, 0x139 },


  { 0x9002f, 0x8 },


  { 0x90030, 0x478 },


  { 0x90031, 0x109 },


  { 0x90032, 0x0 },


  { 0x90033, 0xe8 },


  { 0x90034, 0x109 },


  { 0x90035, 0x2 },


  { 0x90036, 0x10 },


  { 0x90037, 0x139 },


  { 0x90038, 0xb },


  { 0x90039, 0x7c0 },


  { 0x9003a, 0x139 },


  { 0x9003b, 0x44 },


  { 0x9003c, 0x633 },


  { 0x9003d, 0x159 },


  { 0x9003e, 0x14f },


  { 0x9003f, 0x630 },


  { 0x90040, 0x159 },


  { 0x90041, 0x47 },


  { 0x90042, 0x633 },


  { 0x90043, 0x149 },


  { 0x90044, 0x4f },


  { 0x90045, 0x633 },


  { 0x90046, 0x179 },


  { 0x90047, 0x8 },


  { 0x90048, 0xe0 },


  { 0x90049, 0x109 },


  { 0x9004a, 0x0 },


  { 0x9004b, 0x7c8 },


  { 0x9004c, 0x109 },


  { 0x9004d, 0x0 },


  { 0x9004e, 0x1 },


  { 0x9004f, 0x8 },


  { 0x90050, 0x0 },


  { 0x90051, 0x45a },


  { 0x90052, 0x9 },


  { 0x90053, 0x0 },


  { 0x90054, 0x448 },


  { 0x90055, 0x109 },


  { 0x90056, 0x40 },


  { 0x90057, 0x633 },


  { 0x90058, 0x179 },


  { 0x90059, 0x1 },


  { 0x9005a, 0x618 },


  { 0x9005b, 0x109 },


  { 0x9005c, 0x40c0 },


  { 0x9005d, 0x633 },


  { 0x9005e, 0x149 },


  { 0x9005f, 0x8 },


  { 0x90060, 0x4 },


  { 0x90061, 0x48 },


  { 0x90062, 0x4040 },


  { 0x90063, 0x633 },


  { 0x90064, 0x149 },


  { 0x90065, 0x0 },


  { 0x90066, 0x4 },


  { 0x90067, 0x48 },


  { 0x90068, 0x40 },


  { 0x90069, 0x633 },


  { 0x9006a, 0x149 },


  { 0x9006b, 0x10 },


  { 0x9006c, 0x4 },


  { 0x9006d, 0x18 },


  { 0x9006e, 0x0 },


  { 0x9006f, 0x4 },


  { 0x90070, 0x78 },


  { 0x90071, 0x549 },


  { 0x90072, 0x633 },


  { 0x90073, 0x159 },


  { 0x90074, 0xd49 },


  { 0x90075, 0x633 },


  { 0x90076, 0x159 },


  { 0x90077, 0x94a },


  { 0x90078, 0x633 },


  { 0x90079, 0x159 },


  { 0x9007a, 0x441 },


  { 0x9007b, 0x633 },


  { 0x9007c, 0x149 },


  { 0x9007d, 0x42 },


  { 0x9007e, 0x633 },


  { 0x9007f, 0x149 },


  { 0x90080, 0x1 },


  { 0x90081, 0x633 },


  { 0x90082, 0x149 },


  { 0x90083, 0x0 },


  { 0x90084, 0xe0 },


  { 0x90085, 0x109 },


  { 0x90086, 0xa },


  { 0x90087, 0x10 },


  { 0x90088, 0x109 },


  { 0x90089, 0x9 },


  { 0x9008a, 0x3c0 },


  { 0x9008b, 0x149 },


  { 0x9008c, 0x9 },


  { 0x9008d, 0x3c0 },


  { 0x9008e, 0x159 },


  { 0x9008f, 0x18 },


  { 0x90090, 0x10 },


  { 0x90091, 0x109 },


  { 0x90092, 0x0 },


  { 0x90093, 0x3c0 },


  { 0x90094, 0x109 },


  { 0x90095, 0x18 },


  { 0x90096, 0x4 },


  { 0x90097, 0x48 },


  { 0x90098, 0x18 },


  { 0x90099, 0x4 },


  { 0x9009a, 0x58 },


  { 0x9009b, 0xb },


  { 0x9009c, 0x10 },


  { 0x9009d, 0x109 },


  { 0x9009e, 0x1 },


  { 0x9009f, 0x10 },


  { 0x900a0, 0x109 },


  { 0x900a1, 0x5 },


  { 0x900a2, 0x7c0 },


  { 0x900a3, 0x109 },


  { 0x40000, 0x811 },


  { 0x40020, 0x880 },


  { 0x40040, 0x0 },


  { 0x40060, 0x0 },


  { 0x40001, 0x4008 },


  { 0x40021, 0x83 },


  { 0x40041, 0x4f },


  { 0x40061, 0x0 },


  { 0x40002, 0x4040 },


  { 0x40022, 0x83 },


  { 0x40042, 0x51 },


  { 0x40062, 0x0 },


  { 0x40003, 0x811 },


  { 0x40023, 0x880 },


  { 0x40043, 0x0 },


  { 0x40063, 0x0 },


  { 0x40004, 0x720 },


  { 0x40024, 0xf },


  { 0x40044, 0x1740 },


  { 0x40064, 0x0 },


  { 0x40005, 0x16 },


  { 0x40025, 0x83 },


  { 0x40045, 0x4b },


  { 0x40065, 0x0 },


  { 0x40006, 0x716 },


  { 0x40026, 0xf },


  { 0x40046, 0x2001 },


  { 0x40066, 0x0 },


  { 0x40007, 0x716 },


  { 0x40027, 0xf },


  { 0x40047, 0x2800 },


  { 0x40067, 0x0 },


  { 0x40008, 0x716 },


  { 0x40028, 0xf },


  { 0x40048, 0xf00 },


  { 0x40068, 0x0 },


  { 0x40009, 0x720 },


  { 0x40029, 0xf },


  { 0x40049, 0x1400 },


  { 0x40069, 0x0 },


  { 0x4000a, 0xe08 },


  { 0x4002a, 0xc15 },


  { 0x4004a, 0x0 },


  { 0x4006a, 0x0 },


  { 0x4000b, 0x625 },


  { 0x4002b, 0x15 },


  { 0x4004b, 0x0 },


  { 0x4006b, 0x0 },


  { 0x4000c, 0x4028 },


  { 0x4002c, 0x80 },


  { 0x4004c, 0x0 },


  { 0x4006c, 0x0 },


  { 0x4000d, 0xe08 },


  { 0x4002d, 0xc1a },


  { 0x4004d, 0x0 },


  { 0x4006d, 0x0 },


  { 0x4000e, 0x625 },


  { 0x4002e, 0x1a },


  { 0x4004e, 0x0 },


  { 0x4006e, 0x0 },


  { 0x4000f, 0x4040 },


  { 0x4002f, 0x80 },


  { 0x4004f, 0x0 },


  { 0x4006f, 0x0 },


  { 0x40010, 0x2604 },


  { 0x40030, 0x15 },


  { 0x40050, 0x0 },


  { 0x40070, 0x0 },


  { 0x40011, 0x708 },


  { 0x40031, 0x5 },


  { 0x40051, 0x0 },


  { 0x40071, 0x2002 },


  { 0x40012, 0x8 },


  { 0x40032, 0x80 },


  { 0x40052, 0x0 },


  { 0x40072, 0x0 },


  { 0x40013, 0x2604 },


  { 0x40033, 0x1a },


  { 0x40053, 0x0 },


  { 0x40073, 0x0 },


  { 0x40014, 0x708 },


  { 0x40034, 0xa },


  { 0x40054, 0x0 },


  { 0x40074, 0x2002 },


  { 0x40015, 0x4040 },


  { 0x40035, 0x80 },


  { 0x40055, 0x0 },


  { 0x40075, 0x0 },


  { 0x40016, 0x60a },


  { 0x40036, 0x15 },


  { 0x40056, 0x1200 },


  { 0x40076, 0x0 },


  { 0x40017, 0x61a },


  { 0x40037, 0x15 },


  { 0x40057, 0x1300 },


  { 0x40077, 0x0 },


  { 0x40018, 0x60a },


  { 0x40038, 0x1a },


  { 0x40058, 0x1200 },


  { 0x40078, 0x0 },


  { 0x40019, 0x642 },


  { 0x40039, 0x1a },


  { 0x40059, 0x1300 },


  { 0x40079, 0x0 },


  { 0x4001a, 0x4808 },


  { 0x4003a, 0x880 },


  { 0x4005a, 0x0 },


  { 0x4007a, 0x0 },


  { 0x900a4, 0x0 },


  { 0x900a5, 0x790 },


  { 0x900a6, 0x11a },


  { 0x900a7, 0x8 },


  { 0x900a8, 0x7aa },


  { 0x900a9, 0x2a },


  { 0x900aa, 0x10 },


  { 0x900ab, 0x7b2 },


  { 0x900ac, 0x2a },


  { 0x900ad, 0x0 },


  { 0x900ae, 0x7c8 },


  { 0x900af, 0x109 },


  { 0x900b0, 0x10 },


  { 0x900b1, 0x10 },


  { 0x900b2, 0x109 },


  { 0x900b3, 0x10 },


  { 0x900b4, 0x2a8 },


  { 0x900b5, 0x129 },


  { 0x900b6, 0x8 },


  { 0x900b7, 0x370 },


  { 0x900b8, 0x129 },


  { 0x900b9, 0xa },


  { 0x900ba, 0x3c8 },


  { 0x900bb, 0x1a9 },


  { 0x900bc, 0xc },


  { 0x900bd, 0x408 },


  { 0x900be, 0x199 },


  { 0x900bf, 0x14 },


  { 0x900c0, 0x790 },


  { 0x900c1, 0x11a },


  { 0x900c2, 0x8 },


  { 0x900c3, 0x4 },


  { 0x900c4, 0x18 },


  { 0x900c5, 0xe },


  { 0x900c6, 0x408 },


  { 0x900c7, 0x199 },


  { 0x900c8, 0x8 },


  { 0x900c9, 0x8568 },


  { 0x900ca, 0x108 },


  { 0x900cb, 0x18 },


  { 0x900cc, 0x790 },


  { 0x900cd, 0x16a },


  { 0x900ce, 0x8 },


  { 0x900cf, 0x1d8 },


  { 0x900d0, 0x169 },


  { 0x900d1, 0x10 },


  { 0x900d2, 0x8558 },


  { 0x900d3, 0x168 },


  { 0x900d4, 0x70 },


  { 0x900d5, 0x788 },


  { 0x900d6, 0x16a },


  { 0x900d7, 0x1ff8 },


  { 0x900d8, 0x85a8 },


  { 0x900d9, 0x1e8 },


  { 0x900da, 0x50 },


  { 0x900db, 0x798 },


  { 0x900dc, 0x16a },


  { 0x900dd, 0x60 },


  { 0x900de, 0x7a0 },


  { 0x900df, 0x16a },


  { 0x900e0, 0x8 },


  { 0x900e1, 0x8310 },


  { 0x900e2, 0x168 },


  { 0x900e3, 0x8 },


  { 0x900e4, 0xa310 },


  { 0x900e5, 0x168 },


  { 0x900e6, 0xa },


  { 0x900e7, 0x408 },


  { 0x900e8, 0x169 },


  { 0x900e9, 0x6e },


  { 0x900ea, 0x0 },


  { 0x900eb, 0x68 },


  { 0x900ec, 0x0 },


  { 0x900ed, 0x408 },


  { 0x900ee, 0x169 },


  { 0x900ef, 0x0 },


  { 0x900f0, 0x8310 },


  { 0x900f1, 0x168 },


  { 0x900f2, 0x0 },


  { 0x900f3, 0xa310 },


  { 0x900f4, 0x168 },


  { 0x900f5, 0x1ff8 },


  { 0x900f6, 0x85a8 },


  { 0x900f7, 0x1e8 },


  { 0x900f8, 0x68 },


  { 0x900f9, 0x798 },


  { 0x900fa, 0x16a },


  { 0x900fb, 0x78 },


  { 0x900fc, 0x7a0 },


  { 0x900fd, 0x16a },


  { 0x900fe, 0x68 },


  { 0x900ff, 0x790 },


  { 0x90100, 0x16a },


  { 0x90101, 0x8 },


  { 0x90102, 0x8b10 },


  { 0x90103, 0x168 },


  { 0x90104, 0x8 },


  { 0x90105, 0xab10 },


  { 0x90106, 0x168 },


  { 0x90107, 0xa },


  { 0x90108, 0x408 },


  { 0x90109, 0x169 },


  { 0x9010a, 0x58 },


  { 0x9010b, 0x0 },


  { 0x9010c, 0x68 },


  { 0x9010d, 0x0 },


  { 0x9010e, 0x408 },


  { 0x9010f, 0x169 },


  { 0x90110, 0x0 },


  { 0x90111, 0x8b10 },


  { 0x90112, 0x168 },


  { 0x90113, 0x0 },


  { 0x90114, 0xab10 },


  { 0x90115, 0x168 },


  { 0x90116, 0x0 },


  { 0x90117, 0x1d8 },


  { 0x90118, 0x169 },


  { 0x90119, 0x80 },


  { 0x9011a, 0x790 },


  { 0x9011b, 0x16a },


  { 0x9011c, 0x18 },


  { 0x9011d, 0x7aa },


  { 0x9011e, 0x6a },


  { 0x9011f, 0xa },


  { 0x90120, 0x0 },


  { 0x90121, 0x1e9 },


  { 0x90122, 0x8 },


  { 0x90123, 0x8080 },


  { 0x90124, 0x108 },


  { 0x90125, 0xf },


  { 0x90126, 0x408 },


  { 0x90127, 0x169 },


  { 0x90128, 0xc },


  { 0x90129, 0x0 },


  { 0x9012a, 0x68 },


  { 0x9012b, 0x9 },


  { 0x9012c, 0x0 },


  { 0x9012d, 0x1a9 },


  { 0x9012e, 0x0 },


  { 0x9012f, 0x408 },


  { 0x90130, 0x169 },


  { 0x90131, 0x0 },


  { 0x90132, 0x8080 },


  { 0x90133, 0x108 },


  { 0x90134, 0x8 },


  { 0x90135, 0x7aa },


  { 0x90136, 0x6a },


  { 0x90137, 0x0 },


  { 0x90138, 0x8568 },


  { 0x90139, 0x108 },


  { 0x9013a, 0xb7 },


  { 0x9013b, 0x790 },


  { 0x9013c, 0x16a },


  { 0x9013d, 0x1f },


  { 0x9013e, 0x0 },


  { 0x9013f, 0x68 },


  { 0x90140, 0x8 },


  { 0x90141, 0x8558 },


  { 0x90142, 0x168 },


  { 0x90143, 0xf },


  { 0x90144, 0x408 },


  { 0x90145, 0x169 },


  { 0x90146, 0xd },


  { 0x90147, 0x0 },


  { 0x90148, 0x68 },


  { 0x90149, 0x0 },


  { 0x9014a, 0x408 },


  { 0x9014b, 0x169 },


  { 0x9014c, 0x0 },


  { 0x9014d, 0x8558 },


  { 0x9014e, 0x168 },


  { 0x9014f, 0x8 },


  { 0x90150, 0x3c8 },


  { 0x90151, 0x1a9 },


  { 0x90152, 0x3 },


  { 0x90153, 0x370 },


  { 0x90154, 0x129 },


  { 0x90155, 0x20 },


  { 0x90156, 0x2aa },


  { 0x90157, 0x9 },


  { 0x90158, 0x0 },


  { 0x90159, 0x400 },


  { 0x9015a, 0x10e },


  { 0x9015b, 0x8 },


  { 0x9015c, 0xe8 },


  { 0x9015d, 0x109 },


  { 0x9015e, 0x0 },


  { 0x9015f, 0x8140 },


  { 0x90160, 0x10c },


  { 0x90161, 0x10 },


  { 0x90162, 0x8138 },


  { 0x90163, 0x10c },


  { 0x90164, 0x8 },


  { 0x90165, 0x7c8 },


  { 0x90166, 0x101 },


  { 0x90167, 0x8 },


  { 0x90168, 0x448 },


  { 0x90169, 0x109 },


  { 0x9016a, 0xf },


  { 0x9016b, 0x7c0 },


  { 0x9016c, 0x109 },


  { 0x9016d, 0x0 },


  { 0x9016e, 0xe8 },


  { 0x9016f, 0x109 },


  { 0x90170, 0x47 },


  { 0x90171, 0x630 },


  { 0x90172, 0x109 },


  { 0x90173, 0x8 },


  { 0x90174, 0x618 },


  { 0x90175, 0x109 },


  { 0x90176, 0x8 },


  { 0x90177, 0xe0 },


  { 0x90178, 0x109 },


  { 0x90179, 0x0 },


  { 0x9017a, 0x7c8 },


  { 0x9017b, 0x109 },


  { 0x9017c, 0x8 },


  { 0x9017d, 0x8140 },


  { 0x9017e, 0x10c },


  { 0x9017f, 0x0 },


  { 0x90180, 0x1 },


  { 0x90181, 0x8 },


  { 0x90182, 0x8 },


  { 0x90183, 0x4 },


  { 0x90184, 0x8 },


  { 0x90185, 0x8 },


  { 0x90186, 0x7c8 },


  { 0x90187, 0x101 },


  { 0x90006, 0x0 },


  { 0x90007, 0x0 },


  { 0x90008, 0x8 },


  { 0x90009, 0x0 },


  { 0x9000a, 0x0 },


  { 0x9000b, 0x0 },


  { 0xd00e7, 0x400 },


  { 0x90017, 0x0 },


  { 0x9001f, 0x29 },


  { 0x90026, 0x6a },


  { 0x400d0, 0x0 },


  { 0x400d1, 0x101 },


  { 0x400d2, 0x105 },


  { 0x400d3, 0x107 },


  { 0x400d4, 0x10f },


  { 0x400d5, 0x202 },


  { 0x400d6, 0x20a },


  { 0x400d7, 0x20b },


  { 0x2003a, 0x2 },


  { 0x2000b, 0x64 },


  { 0x2000c, 0xc8 },


  { 0x2000d, 0x7d0 },


  { 0x2000e, 0x2c },


  { 0x12000b, 0xc },


  { 0x12000c, 0x19 },


  { 0x12000d, 0xfa },


  { 0x12000e, 0x10 },


  { 0x22000b, 0x3 },


  { 0x22000c, 0x6 },


  { 0x22000d, 0x3e },


  { 0x22000e, 0x10 },


  { 0x9000c, 0x0 },


  { 0x9000d, 0x173 },


  { 0x9000e, 0x60 },


  { 0x9000f, 0x6110 },


  { 0x90010, 0x2152 },


  { 0x90011, 0xdfbd },


  { 0x90012, 0x2060 },


  { 0x90013, 0x6152 },


  { 0x20010, 0x5a },


  { 0x20011, 0x3 },


  { 0x40080, 0xe0 },


  { 0x40081, 0x12 },


  { 0x40082, 0xe0 },


  { 0x40083, 0x12 },


  { 0x40084, 0xe0 },


  { 0x40085, 0x12 },


  { 0x140080, 0xe0 },


  { 0x140081, 0x12 },


  { 0x140082, 0xe0 },


  { 0x140083, 0x12 },


  { 0x140084, 0xe0 },


  { 0x140085, 0x12 },


  { 0x240080, 0xe0 },


  { 0x240081, 0x12 },


  { 0x240082, 0xe0 },


  { 0x240083, 0x12 },


  { 0x240084, 0xe0 },


  { 0x240085, 0x12 },


  { 0x400fd, 0xf },


  { 0x10011, 0x1 },


  { 0x10012, 0x1 },


  { 0x10013, 0x180 },


  { 0x10018, 0x1 },


  { 0x10002, 0x6209 },


  { 0x100b2, 0x1 },


  { 0x101b4, 0x1 },


  { 0x102b4, 0x1 },


  { 0x103b4, 0x1 },


  { 0x104b4, 0x1 },


  { 0x105b4, 0x1 },


  { 0x106b4, 0x1 },


  { 0x107b4, 0x1 },


  { 0x108b4, 0x1 },


  { 0x11011, 0x1 },


  { 0x11012, 0x1 },


  { 0x11013, 0x180 },


  { 0x11018, 0x1 },


  { 0x11002, 0x6209 },


  { 0x110b2, 0x1 },


  { 0x111b4, 0x1 },


  { 0x112b4, 0x1 },


  { 0x113b4, 0x1 },


  { 0x114b4, 0x1 },


  { 0x115b4, 0x1 },


  { 0x116b4, 0x1 },


  { 0x117b4, 0x1 },


  { 0x118b4, 0x1 },


  { 0x20089, 0x1 },


  { 0x20088, 0x19 },


  { 0xc0080, 0x2 },


  { 0xd0000, 0x1 }



+};



+struct dram_fsp_msg ddr_dram_fsp_msg[] = {

  {


          /* P0 3200mts 1D */


          .drate = 3200,


          .fw_type = FW_1D_IMAGE,


          .fsp_cfg = ddr_fsp0_cfg,


          .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),


  },


  {


          /* P1 400mts 1D */


          .drate = 400,


          .fw_type = FW_1D_IMAGE,


          .fsp_cfg = ddr_fsp1_cfg,


          .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),


  },


  {


          /* P2 100mts 1D */


          .drate = 100,


          .fw_type = FW_1D_IMAGE,


          .fsp_cfg = ddr_fsp2_cfg,


          .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),


  },


  {


          /* P0 3200mts 2D */


          .drate = 3200,


          .fw_type = FW_2D_IMAGE,


          .fsp_cfg = ddr_fsp0_2d_cfg,


          .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),


  },



+};



+/* ddr timing config params */
+struct dram_timing_info dram_timing = {

  .ddrc_cfg = ddr_ddrc_cfg,


  .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),


  .ddrphy_cfg = ddr_ddrphy_cfg,


  .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),


  .fsp_msg = ddr_dram_fsp_msg,


  .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),


  .ddrphy_trained_csr = ddr_ddrphy_trained_csr,


  .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),


  .ddrphy_pie = ddr_phy_pie,


  .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),


  .fsp_table = { 3200, 400, 100, },



+};



diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
new file mode 100644
index 0000000000..6f076f5445
--- /dev/null
+++ b/board/beacon/imx8mn/spl.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2020 Compass Electronics Group, LLC


*/


+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mn_pins.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/bd71837.h>
+#include <spl.h>



+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>



+DECLARE_GLOBAL_DATA_PTR;



+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{

  return BOOT_DEVICE_BOOTROM;



+}



+void spl_dram_init(void)
+{

  ddr_init(&dram_timing);



+}



+void spl_board_init(void)
+{

  struct udevice *dev;


  int ret;



  debug("Normal Boot\n");



  ret = uclass_get_device_by_name(UCLASS_CLK,


                                  "clock-controller@30380000",


                                  &dev);


  if (ret < 0)


          puts("Failed to find clock node. Check device tree\n");



+}



+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{

  /* Just empty function now - can't decide what to choose */


  debug("%s: %s\n", __func__, name);



  return 0;



+}
+#endif



+#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+#define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)



+static iomux_v3_cfg_t const pwm_pads[] = {

  IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),



+};



+static iomux_v3_cfg_t const uart_pads[] = {

  IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),


  IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),



+};



+static iomux_v3_cfg_t const wdog_pads[] = {

  IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),



+};



+int board_early_init_f(void)
+{

  struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;



  /* Claiming pwm pins prevents LCD flicker during startup*/


  imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));



  imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));


  set_wdog_reset(wdog);



  imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));


  init_uart_clk(1);



  return 0;



+}



+void board_init_f(ulong dummy)
+{

  int ret;



  /* Clear the BSS. */


  memset(__bss_start, 0, __bss_end - __bss_start);



  arch_cpu_init();



  board_early_init_f();



  timer_init();



  preloader_console_init();



  ret = spl_init();


  if (ret) {


          debug("spl_init() failed: %d\n", ret);


          hang();


  }



  /* DDR initialization */


  spl_dram_init();



  board_init_r(NULL, 0);



+}
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
new file mode 100644
index 0000000000..d6a3385d8d
--- /dev/null
+++ b/configs/imx8mn_beacon_defconfig
@@ -0,0 +1,132 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x44000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_TARGET_IMX8MN_BEACON=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_BD71837=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x0
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
new file mode 100644
index 0000000000..7a247cc560
--- /dev/null
+++ b/include/configs/imx8mn_beacon.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*


Copyright 2020 Compass Electronics Group, LLC


*/


+#ifndef __IMX8MN_BEACON_H
+#define __IMX8MN_BEACON_H



+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>



+#define CONFIG_SPL_MAX_SIZE            (148 * SZ_1K)
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR        0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
+#define CONFIG_SYS_UBOOT_BASE  \

  (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)




+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK               0x187FF0
+#define CONFIG_SPL_BSS_START_ADDR      0x0095e000
+#define CONFIG_SPL_BSS_MAX_SIZE        SZ_8K
+#define CONFIG_SYS_SPL_MALLOC_START    0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     SZ_512K



+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR           0x184000



+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE



+#endif /* CONFIG_SPL_BUILD */



+#define CONFIG_REMAKE_ELF



+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS              \

  "script=boot.scr\0" \


  "image=Image\0" \


  "ramdiskimage=rootfs.cpio.uboot\0" \


  "console=ttymxc1,115200\0" \


  "fdt_addr=0x43000000\0"                 \


  "ramdisk_addr=0x44000000\0" \


  "boot_fdt=try\0" \


  "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \


  "initrd_addr=0x43800000\0"              \


  "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \


  "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \


  "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \


  "mmcautodetect=yes\0" \


  "mmcargs=setenv bootargs console=${console} " \


  " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \


  "ramargs=setenv bootargs console=${console} root=/dev/ram rw " \


  " ${optargs}\0" \


  "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \


  "bootscript=echo Running bootscript from mmc ...; " \


          "source\0" \


  "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \


  "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \


  "loadramdisk=load mmc ${mmcdev} ${ramdisk_addr} ${ramdiskimage}\0"\


  "mmcboot=echo Booting from mmc ...; " \


          "run finduuid; run mmcargs; " \


          "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \


                  "if run loadfdt; then " \


                          "booti ${loadaddr} - ${fdt_addr}; " \


                  "else " \


                          "echo WARN: Cannot load the DT; " \


                  "fi; " \


          "else " \


                  "echo wait for boot; " \


          "fi;\0" \


  "netargs=setenv bootargs console=${console} " \


          "root=/dev/nfs " \


          "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \


  "netboot=echo Booting from net ...; " \


          "run netargs;  " \


          "if test ${ip_dyn} = yes; then " \


                  "setenv get_cmd dhcp; " \


          "else " \


                  "setenv get_cmd tftp; " \


          "fi; " \


          "${get_cmd} ${loadaddr} ${image}; " \


          "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \


                  "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \


                          "booti ${loadaddr} - ${fdt_addr}; " \


                  "else " \


                          "echo WARN: Cannot load the DT; " \


                  "fi; " \


          "else " \


                  "booti; " \


          "fi;\0" \


  "ramboot=echo Booting from RAMdisk...; "\


          "run loadimage; run loadfdt; fdt addr $fdt_addr; "\


          "run loadramdisk; run ramargs; " \


          "booti ${loadaddr} ${ramdisk_addr} ${fdt_addr} ${optargs}\0"




+#define CONFIG_BOOTCOMMAND \

     "mmc dev ${mmcdev}; if mmc rescan; then " \


             "if run loadbootscript; then " \


                     "run bootscript; " \


             "else " \


                     "if run loadimage; then " \


                             "run mmcboot; " \


                     "else run netboot; " \


                     "fi; " \


             "fi; " \


     "else booti ${loadaddr} - ${fdt_addr}; fi"




+/* Link Definitions */
+#define CONFIG_LOADADDR                        0x40480000



+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR



+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x200000
+#define CONFIG_SYS_INIT_SP_OFFSET \

  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)



+#define CONFIG_SYS_INIT_SP_ADDR \

  (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)




+#define CONFIG_ENV_OVERWRITE



+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          SZ_32M



+#define CONFIG_SYS_SDRAM_BASE          0x40000000
+#define PHYS_SDRAM                     0x40000000
+#define PHYS_SDRAM_SIZE                0x40000000 /* 1GB DDR */



+#define CONFIG_MXC_UART_BASE           UART2_BASE_ADDR



+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \

                                  sizeof(CONFIG_SYS_PROMPT) + 16)




+/* USDHC */
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_MMC_IMG_LOAD_PART   1



+/* ENET Config */
+#if defined(CONFIG_FEC_MXC)
+#define CONFIG_ETHPRIME                "FEC"
+#define CONFIG_FEC_XCV_TYPE            RGMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define FEC_QUIRK_ENET_MAC
+#define IMX_FEC_BASE                   0x30BE0000
+#endif /* CONFIG_FEC_MXC */



+#endif
2.25.1

    