-----Original Message----- From: Horia Geanta Sent: Wednesday, July 25, 2018 11:25 PM To: Laurentiu Tudor laurentiu.tudor@nxp.com; York Sun york.sun@nxp.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de Cc: Bharat Bhushan bharat.bhushan@nxp.com Subject: Re: [PATCH v4 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device tree
On 7/24/2018 5:05 PM, laurentiu.tudor@nxp.com wrote:
From: Laurentiu Tudor laurentiu.tudor@nxp.com
Add support for SEC ICID configuration and apply it for ls1046a. Also add code to make the necessary device tree fixups. Also included in this patch, while adding the new required JR defines sanitize the preexisting ones by dropping the CONFIG_ prefixes.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com
.../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 15 ++++++++++++ .../asm/arch-fsl-layerscape/fsl_icid.h | 24 +++++++++++++++++++ .../asm/arch-fsl-layerscape/immap_lsch2.h | 11 ++++++--- drivers/crypto/fsl/jr.c | 2 +- scripts/config_whitelist.txt | 2 -- 5 files changed, 48 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 30c7d8d28a..84f7665929 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -7,6 +7,7 @@ #include <asm/arch-fsl-layerscape/immap_lsch2.h> #include <asm/arch-fsl-layerscape/fsl_icid.h> #include <asm/arch-fsl-layerscape/fsl_portals.h> +#include <fsl_sec.h>
The header should be included where it's used, in fsl_icid.h.
#ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { @@ -40,6 +41,20 @@ struct icid_id_table icid_tbl[] = { SET_EDMA_ICID(FSL_EDMA_STREAM_ID), SET_ETR_ICID(FSL_ETR_STREAM_ID), SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID), +#ifdef CONFIG_FSL_CAAM
- SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
- SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 2),
- SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 2),
- SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 2),
- SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 2),
- SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 2),
- SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 2),
- SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 2),
- SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 2),
- SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 2),
- SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 2),
- SET_SEC_DECO_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 2),
+#endif };
PPA firmware running in secure world is using JR3 (what sec_firmware_used_jobring_offset() returns). I think a different ICID should be allocated for it, considering it has different security requirements.
All JR interfaces should be assigned different ICID. While I am not sure DECO and RTIC are separate devices and can be used by software independently from JR interface.
BTW, is it clear that U-boot is responsible for ICID programming, and not PPA?
We can still boot without PPA/ATF, so keeping in u-boot is good at least for now. I know about the new ATF architecture and stuff.
int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 5be50a17ab..bd613219b6 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -82,6 +82,30 @@ void fdt_fixup_icid(void *blob); #define SET_FMAN_ICID_ENTRY(_port_id, streamid) \ { .port_id = (_port_id), .icid = (streamid) }
+#define SET_SEC_QI_ICID(streamid) \
- SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
(((streamid) << 16) | (streamid)), \offsetof(struct ccsr_sec, qilcr_ls) + \s/struct ccsr_sec/ccsr_sec_t
CONFIG_SYS_FSL_SEC_ADDR, \CONFIG_SYS_FSL_SEC_ADDR)+#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
- SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
(((streamid) << 16) | (streamid)), \offsetof(struct ccsr_sec, jrliodnr[jr_num].ls) + \CONFIG_SYS_FSL_SEC_ADDR, \FSL_SEC_JR##jr_num##_BASE_ADDR)+#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
- SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
offsetof(struct ccsr_sec, decoliodnr[deco_num].ls) + \CONFIG_SYS_FSL_SEC_ADDR, 0)+#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
- SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
offsetof(struct ccsr_sec, rticliodnr[rtic_num].ls) + \CONFIG_SYS_FSL_SEC_ADDR, 0)extern struct icid_id_table icid_tbl[]; extern struct fman_icid_id_table fman_icid_tbl[]; extern int icid_tbl_sz; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d22ec70aa5..0dd09a5d81 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -199,11 +199,16 @@ struct sys_info { (CONFIG_SYS_IMMR +
CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull -#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull +#define FSL_SEC_JR0_OFFSET 0x710000ull +#define FSL_SEC_JR1_OFFSET 0x720000ull +#define FSL_SEC_JR2_OFFSET 0x730000ull +#define FSL_SEC_JR3_OFFSET 0x740000ull #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) -#define CONFIG_SYS_FSL_JR0_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR +
FSL_SEC_JR0_OFFSET)
+#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR +
FSL_SEC_JR1_OFFSET)
+#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR +
FSL_SEC_JR2_OFFSET)
+#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR +
FSL_SEC_JR3_OFFSET)
/* Device Configuration and Pin Control */ #define DCFG_DCSR_PORCR1 0x0 diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index cc8d3b02a5..f06d7a6635 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -31,7 +31,7 @@ uint32_t
sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
#define SEC_JR0_ADDR(idx) \ (SEC_ADDR(idx) + \
(CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
(FSL_SEC_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))This will break all the other users of the driver (ppc, armv8 dpaa2, i.mx) since FSL_SEC_JR0_OFFSET is defined only in immap_lsch2.h.
Regards, Horia