Re: [U-Boot] [PATCH] ARM: non-sec: flush code cacheline aligned

3 Aug 2016


      Hi Stefan,
On Wed, Aug 3, 2016 at 5:08 PM, Stefan Agner stefan@agner.ch wrote:
...
From: Stefan Agner stefan.agner@toradex.com
Flush operations need to be cacheline aligned to take effect, make
sure to flush always complete cachelines. This avoids messages such
as:
CACHE: Misaligned operation at range [00900000, 009004d9]
Signed-off-by: Stefan Agner stefan.agner@toradex.com
This fixes the cache warnings:
Tested-by: Fabio Estevam fabio.estevam@nxp.com
Thanks