The HDMI PHY depends on the HVCC supply being enabled. So far we have relied on it being enabled by an earlier firmware stage (SPL or TF-A). Attempt to enable the regulator here, so we can remove that dependency.
Signed-off-by: Samuel Holland samuel@sholland.org ---
drivers/video/sunxi/sunxi_dw_hdmi.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 04588b570fd..963689358a6 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -19,6 +19,7 @@ #include <asm/arch/lcdc.h> #include <linux/bitops.h> #include <linux/delay.h> +#include <power/regulator.h>
struct sunxi_dw_hdmi_priv { struct dw_hdmi hdmi; @@ -331,8 +332,13 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; struct reset_ctl_bulk resets; struct clk_bulk clocks; + struct udevice *hvcc; int ret;
+ ret = device_get_supply_regulator(dev, "hvcc-supply", &hvcc); + if (!ret) + regulator_set_enable(hvcc, true); + /* Set pll3 to 297 MHz */ clock_set_pll3(297000000);