Re: [U-Boot] [PATCH 1/2] LPC2468 support

19 Mar 2009

Wolfgang Denk schreef:
...
...
+/* Vectored Interrupt Controller (VIC) */
+#define VIC_BASE_ADDR	0xFFFFF000
+#define VICIRQStatus   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000))
+#define VICFIQStatus   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004))
+#define VICRawIntr     (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008))
+#define VICIntSelect   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C))
+#define VICIntEnable   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010))
+#define VICIntEnClr    (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014))
+#define VICSoftInt     (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018))
+#define VICSoftIntClr  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C))
+#define VICProtection  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020))
+#define VICSWPrioMask  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024))
Please do not use offset lists, but define a proper C data  structure
instead.  And  never  ever  access  device  regiters  through  simple
volatile pointers. Use proper accessor functions. Here and elsewhere.
Hi,
All examples I checked use the same syntax for defining registers, so I left it
in the code. If that is a problem, can you indicate an example which does The Right Thing (tm)?
...
The whole code needs a *major* cleanup before resubmitting.
I think the patch now matches the other criteria. The patch is a bit bigger, since
other code did not follow the Coding Styles either. I used indent to fix my code and it fixed the other code as well.
The second patch will follow when this patch is OK.
Regards,
Remco Poelstra
----

--- u-boot-orig/cpu/arm720t/cpu.c	2009-03-18 00:42:12.000000000 +0100
+++ u-boot/cpu/arm720t/cpu.c	2009-03-19 16:00:04.000000000 +0100
@@ -41,7 +41,9 @@ int cpu_init (void)
     * setup up stacks if necessary
     */
  #ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
+	IRQ_STACK_START =
+	    _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE -
+	    4;
    FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
  #endif
    return 0;
@@ -63,17 +65,17 @@ int cleanup_before_linux (void)
    disable_interrupts ();
/* turn off I-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+      asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
    i &= ~0x1000;
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+      asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
/* flush I-cache */
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+      asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
  #ifdef CONFIG_ARM7_REVD
    /* go to high speed */
    IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
  #endif
-#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)
+#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)|| defined(CONFIG_LPC2468)
    disable_interrupts ();
    /* Nothing more needed */
  #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
@@ -84,12 +86,11 @@ int cleanup_before_linux (void)
    return 0;
  }
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
  {
    disable_interrupts ();
    reset_cpu (0);
-	/*NOTREACHED*/
-	return (0);
+	 /*NOTREACHED*/ return (0);
  }
/*
@@ -99,30 +100,26 @@ int do_reset (cmd_tbl_t *cmdtp, int flag
#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
  /* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1(void)
+static unsigned long read_p15_c1 (void)
  {
    unsigned long value;
-	__asm__ __volatile__(
-		"mrc     p15, 0, %0, c1, c0, 0   @ read control reg\n"
-		: "=r" (value)
-		:
-		: "memory");
+      __asm__ __volatile__ ("mrc     p15, 0, %0, c1, c0, 0   @ read control reg\n":"=r" (value)
+			      ::"memory");
    /* printf("p15/c1 is = %08lx\n", value); */
    return value;
  }
/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1(unsigned long value)
+static void write_p15_c1 (unsigned long value)
  {
    /* printf("write %08lx to p15/c1\n", value); */
-	__asm__ __volatile__(
-		"mcr     p15, 0, %0, c1, c0, 0   @ write it back\n"
-		:
-		: "r" (value)
-		: "memory");
+	__asm__
+	    __volatile__
+	    ("mcr     p15, 0, %0, c1, c0, 0   @ write it back\n"::"r" (value)
+      :     "memory");
-	read_p15_c1();
+	read_p15_c1 ();
  }
static void cp_delay (void)
@@ -130,7 +127,7 @@ static void cp_delay (void)
    volatile int i;
/* copro seems to need some delay between reading and writing */
-	for (i = 0; i < 100; i++);
+	for (i = 0; i < 100; i++) ;
  }
/* See also ARM Ref. Man. */
@@ -196,63 +193,63 @@ void icache_enable (void)
    s32 i;
/* disable all cache bits */
-	CLR_REG( REG_SYSCFG, 0x3F);
+	CLR_REG (REG_SYSCFG, 0x3F);
/* 8KB cache, write enable */
-	SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
+	SET_REG (REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
/* clear TAG RAM bits */
-	for ( i = 0; i < 256; i++)
-	  PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
+	for (i = 0; i < 256; i++)
+		PUT_REG (CACHE_TAG_RAM + 4 * i, 0x00000000);
/* clear SET0 RAM */
-	for(i=0; i < 1024; i++)
-	  PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
+	for (i = 0; i < 1024; i++)
+		PUT_REG (CACHE_SET0_RAM + 4 * i, 0x00000000);
/* clear SET1 RAM */
-	for(i=0; i < 1024; i++)
-	  PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
+	for (i = 0; i < 1024; i++)
+		PUT_REG (CACHE_SET1_RAM + 4 * i, 0x00000000);
/* enable cache */
-	SET_REG( REG_SYSCFG, CACHE_ENABLE);
+	SET_REG (REG_SYSCFG, CACHE_ENABLE);
}
void icache_disable (void)
  {
    /* disable all cache bits */
-	CLR_REG( REG_SYSCFG, 0x3F);
+	CLR_REG (REG_SYSCFG, 0x3F);
  }
int icache_status (void)
  {
-	return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
+	return GET_REG (REG_SYSCFG) & CACHE_ENABLE;
  }
void dcache_enable (void)
  {
    /* we don't have seperate instruction/data caches */
-	icache_enable();
+	icache_enable ();
  }
void dcache_disable (void)
  {
    /* we don't have seperate instruction/data caches */
-	icache_disable();
+	icache_disable ();
  }
int dcache_status (void)
  {
    /* we don't have seperate instruction/data caches */
-	return icache_status();
+	return icache_status ();
  }
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
    /* No specific cache setup for IntegratorAP/CM720T as yet */
-	void icache_enable (void)
-	{
-	}
-#elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */
+void icache_enable (void)
+{
+}
+#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)	/* just to satisfy the compiler */
  #else
  #error No icache/dcache enable/disable functions defined for this CPU type
  #endif
diff -upNr u-boot-orig/cpu/arm720t/interrupts.c u-boot/cpu/arm720t/interrupts.c
--- u-boot-orig/cpu/arm720t/interrupts.c	2009-03-18 00:42:12.000000000 +0100
+++ u-boot/cpu/arm720t/interrupts.c	2009-03-19 15:11:29.000000000 +0100
@@ -40,6 +40,11 @@
  #ifdef CONFIG_LPC2292
  #undef READ_TIMER
  #define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
+#elif defined(CONFIG_LPC2468)
+#undef TIMER_LOAD_VAL
+#define TIMER_LOAD_VAL 0
+#undef READ_TIMER
+#define READ_TIMER (0xFFFFFFFF - T0TC)
  #endif
#else
@@ -57,7 +62,7 @@
  # else
  static struct _irq_handler IRQ_HANDLER[N_IRQS];
  # endif
-#endif	/* CONFIG_S3C4510B */
+#endif /* CONFIG_S3C4510B */
#ifdef CONFIG_USE_IRQ
  void do_irq (struct pt_regs *pt_regs)
@@ -65,21 +70,22 @@ void do_irq (struct pt_regs *pt_regs)
  #if defined(CONFIG_S3C4510B)
    unsigned int pending;
-	while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) {  /* sentinal value for no pending interrutps */
-		IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
+	while ((pending = GET_REG (REG_INTOFFSET)) != 0x54) {	/* sentinal value for no pending interrutps */
+		IRQ_HANDLER[pending >> 2].m_func (IRQ_HANDLER[pending >> 2].
+						  m_data);
/* clear pending interrupt */
-		PUT_REG( REG_INTPEND, (1<<(pending>>2)));
+		PUT_REG (REG_INTPEND, (1 << (pending >> 2)));
    }
  #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
    /* No do_irq() for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
+#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
-    void (*pfnct)(void);
+	void (*pfnct) (void);
-    pfnct = (void (*)(void))VICVectAddr;
+	pfnct = (void (*)(void))VICVectAddr;
-    (*pfnct)();
+	(*pfnct) ();
  #else
  #error do_irq() not defined for this CPU type
  #endif
@@ -87,17 +93,19 @@ void do_irq (struct pt_regs *pt_regs)
  #endif
#ifdef CONFIG_S3C4510B
-static void default_isr( void *data) {
+static void default_isr (void *data)
+{
    printf ("default_isr():  called for IRQ %d\n", (int)data);
  }
-static void timer_isr( void *data) {
+static void timer_isr (void *data)
+{
    unsigned int *pTime = (unsigned int *)data;
(*pTime)++;
-	if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
+	if (!(*pTime % (CONFIG_SYS_HZ / 4))) {
    	/* toggle LED 0 */
-		PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
+		PUT_REG (REG_IOPDATA, GET_REG (REG_IOPDATA) ^ 0x1);
    }
}
@@ -118,9 +126,9 @@ int interrupt_init (void)
    IRQEN = 0;
/* operate timer 2 in non-prescale mode */
-	TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
-		    NETARM_GEN_TCTL_ENABLE |
-		    NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
+	TM2CTRL = (NETARM_GEN_TIMER_SET_HZ (CONFIG_SYS_HZ) |
+		   NETARM_GEN_TCTL_ENABLE |
+		   NETARM_GEN_TCTL_INIT_COUNT (TIMER_LOAD_VAL));
/* set timer 2 counter */
    lastdec = TIMER_LOAD_VAL;
@@ -140,15 +148,15 @@ int interrupt_init (void)
    int i;
/* install default interrupt handlers */
-	for ( i = 0; i < N_IRQS; i++) {
+	for (i = 0; i < N_IRQS; i++) {
    	IRQ_HANDLER[i].m_data = (void *)i;
    	IRQ_HANDLER[i].m_func = default_isr;
    }
/* configure interrupts for IRQ mode */
-	PUT_REG( REG_INTMODE, 0x0);
+	PUT_REG (REG_INTMODE, 0x0);
    /* clear any pending interrupts */
-	PUT_REG( REG_INTPEND, 0x1FFFFF);
+	PUT_REG (REG_INTPEND, 0x1FFFFF);
lastdec = 0;
@@ -157,35 +165,41 @@ int interrupt_init (void)
    IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
/* configure free running timer 0 */
-	PUT_REG( REG_TMOD, 0x0);
+	PUT_REG (REG_TMOD, 0x0);
    /* Stop timer 0 */
-	CLR_REG( REG_TMOD, TM0_RUN);
+	CLR_REG (REG_TMOD, TM0_RUN);
/* Configure for interval mode */
-	CLR_REG( REG_TMOD, TM1_TOGGLE);
+	CLR_REG (REG_TMOD, TM1_TOGGLE);
/*
     * Load Timer data register with count down value.
     * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
     */
-	PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
+	PUT_REG (REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
/*
     * Enable global interrupt
     * Enable timer0 interrupt
     */
-	CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
+	CLR_REG (REG_INTMASK, ((1 << INT_GLOBAL) | (1 << INT_TIMER0)));
/* Start timer */
-	SET_REG( REG_TMOD, TM0_RUN);
+	SET_REG (REG_TMOD, TM0_RUN);
  #elif defined(CONFIG_LPC2292)
-	PUT32(T0IR, 0);		/* disable all timer0 interrupts */
-	PUT32(T0TCR, 0);	/* disable timer0 */
-	PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
-	PUT32(T0MCR, 0);
-	PUT32(T0TC, 0);
-	PUT32(T0TCR, 1);	/* enable timer0 */
-
+	PUT32 (T0IR, 0);	/* disable all timer0 interrupts */
+	PUT32 (T0TCR, 0);	/* disable timer0 */
+	PUT32 (T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
+	PUT32 (T0MCR, 0);
+	PUT32 (T0TC, 0);
+	PUT32 (T0TCR, 1);	/* enable timer0 */
+#elif defined(CONFIG_LPC2468)
+	PUT32 (T0IR, 0);		/*disable all timer0 interupts */
+	PUT32 (T0TCR, 0);		/*disable timer0 */
+	PUT32 (T0PR, CFG_SYS_CLK_FREQ / CONFIG_SYS_HZ - 1);
+	PUT32 (T0MCR, 0);
+	PUT32 (T0TC, 0);
+	PUT32 (T0TCR, 1);
  #else
  #error No interrupt_init() defined for this CPU type
  #endif
@@ -200,8 +214,7 @@ int interrupt_init (void)
   * timer without interrupts
   */
-
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292)
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
void reset_timer (void)
  {
@@ -229,11 +242,11 @@ void udelay (unsigned long usec)
    tmo += get_timer (0);
while (get_timer_masked () < tmo)
-#ifdef CONFIG_LPC2292
+#if defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
    	/* GJ - not sure whether this is really needed or a misunderstanding */
-		__asm__ __volatile__(" nop");
+		__asm__ __volatile__ (" nop");
  #else
-		/*NOP*/;
+		 /*NOP*/;
  #endif
  }
@@ -272,7 +285,7 @@ void udelay_masked (unsigned long usec)
    	tmo /= 1000;
    } else {
    	tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
+		tmo /= (1000 * 1000);
    }
endtime = get_timer_masked () + tmo;
diff -upNr u-boot-orig/cpu/arm720t/lpc24xx/flash.c u-boot/cpu/arm720t/lpc24xx/flash.c
--- u-boot-orig/cpu/arm720t/lpc24xx/flash.c	1970-01-01 01:00:00.000000000 +0100
+++ u-boot/cpu/arm720t/lpc24xx/flash.c	2009-03-19 15:16:57.000000000 +0100
@@ -0,0 +1,232 @@
+/*
+ * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+/* IAP commands use 32 bytes at the top of CPU internal sram, we
+   use 512 bytes below that */
+#define COPY_BUFFER_LOCATION 0x4000fde0
+
+#define IAP_LOCATION 0x7ffffff1
+#define IAP_CMD_PREPARE 50
+#define IAP_CMD_COPY 51
+#define IAP_CMD_ERASE 52
+#define IAP_CMD_CHECK 53
+#define IAP_CMD_ID 54
+#define IAP_CMD_VERSION 55
+#define IAP_CMD_COMPARE 56
+
+#define IAP_RET_CMD_SUCCESS 0
+
+static unsigned long command[5];
+static unsigned long result[2];
+
+extern void iap_entry (unsigned long *command, unsigned long *result);
+
+/*-----------------------------------------------------------------------
+ *
+ */
+int get_flash_sector (flash_info_t * info, ulong flash_addr)
+{
+	int i;
+
+	for (i = 1; i < (info->sector_count); i++) {
+		if (flash_addr < (info->start[i]))
+			break;
+	}
+
+	return (i - 1);
+}
+
+/*-----------------------------------------------------------------------
+ * This function assumes that flash_addr is aligned on 512 bytes boundary
+ * in flash. This function also assumes that prepare have been called
+ * for the sector in question.
+ */
+int lpc24xx_copy_buffer_to_flash (flash_info_t * info, ulong flash_addr)
+{
+	int first_sector;
+	int last_sector;
+
+	first_sector = get_flash_sector (info, flash_addr);
+	last_sector = get_flash_sector (info, flash_addr + 512 - 1);
+
+	/* prepare sectors for write */
+	command[0] = IAP_CMD_PREPARE;
+	command[1] = first_sector;
+	command[2] = last_sector;
+	iap_entry (command, result);
+	if (result[0] != IAP_RET_CMD_SUCCESS) {
+		printf ("IAP prepare failed\n");
+		return ERR_PROG_ERROR;
+	}
+
+	command[0] = IAP_CMD_COPY;
+	command[1] = flash_addr;
+	command[2] = COPY_BUFFER_LOCATION;
+	command[3] = 512;
+	command[4] = CFG_SYS_CLK_FREQ >> 10;
+	iap_entry (command, result);
+	if (result[0] != IAP_RET_CMD_SUCCESS) {
+		printf ("IAP copy failed\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+int lpc24xx_flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag;
+	int prot;
+	int sect;
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	flag = disable_interrupts ();
+
+	printf ("Erasing %d sectors starting at sector %2d.\n"
+		"This make take some time ... ", s_last - s_first + 1, s_first);
+
+	command[0] = IAP_CMD_PREPARE;
+	command[1] = s_first;
+	command[2] = s_last;
+	iap_entry (command, result);
+	if (result[0] != IAP_RET_CMD_SUCCESS) {
+		printf ("IAP prepare failed\n");
+		return ERR_PROTECTED;
+	}
+
+	command[0] = IAP_CMD_ERASE;
+	command[1] = s_first;
+	command[2] = s_last;
+	command[3] = CFG_SYS_CLK_FREQ >> 10;
+	iap_entry (command, result);
+	if (result[0] != IAP_RET_CMD_SUCCESS) {
+		printf ("IAP erase failed\n");
+		return ERR_PROTECTED;
+	}
+
+	if (flag)
+		enable_interrupts ();
+
+	return ERR_OK;
+}
+
+int lpc24xx_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int first_copy_size;
+	int last_copy_size;
+	int first_block;
+	int last_block;
+	int nbr_mid_blocks;
+	uchar memmap_value;
+	ulong i;
+	uchar *src_org;
+	uchar *dst_org;
+	int ret = ERR_OK;
+
+	src_org = src;
+	dst_org = (uchar *) addr;
+
+	first_block = addr / 512;
+	last_block = (addr + cnt) / 512;
+	nbr_mid_blocks = last_block - first_block - 1;
+
+	first_copy_size = 512 - (addr % 512);
+	last_copy_size = (addr + cnt) % 512;
+
+	debug ("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
+	       "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
+	       (ulong) (first_block * 512),
+	       (ulong) COPY_BUFFER_LOCATION,
+	       (ulong) src,
+	       (ulong) (COPY_BUFFER_LOCATION + 512 - first_copy_size),
+	       first_copy_size,
+	       (ulong) COPY_BUFFER_LOCATION, (ulong) (first_block * 512));
+
+	/* copy first block */
+	memcpy ((void *)COPY_BUFFER_LOCATION, (void *)(first_block * 512), 512);
+	memcpy ((void *)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
+		src, first_copy_size);
+	lpc24xx_copy_buffer_to_flash (info, first_block * 512);
+	src += first_copy_size;
+	addr += first_copy_size;
+
+	/* copy middle blocks */
+	for (i = 0; i < nbr_mid_blocks; i++) {
+		debug ("copy middle block: %lX -> %lX 512 bytes, "
+		       "%lX -> %lX 512 bytes\n",
+		       (ulong) src,
+		       (ulong) COPY_BUFFER_LOCATION,
+		       (ulong) COPY_BUFFER_LOCATION, (ulong) addr);
+		memcpy ((void *)COPY_BUFFER_LOCATION, src, 512);
+		lpc24xx_copy_buffer_to_flash (info, addr);
+		src += 512;
+		addr += 512;
+	}
+
+	if (last_copy_size > 0) {
+		debug ("copy last block: (1) %lX -> %lX 0x200 bytes, "
+		       "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
+		       (ulong) (last_block * 512),
+		       (ulong) COPY_BUFFER_LOCATION,
+		       (ulong) src,
+		       (ulong) (COPY_BUFFER_LOCATION),
+		       last_copy_size,
+		       (ulong) COPY_BUFFER_LOCATION, (ulong) addr);
+		/* copy last block */
+		memcpy ((void *)COPY_BUFFER_LOCATION,
+			(void *)(last_block * 512), 512);
+		memcpy ((void *)COPY_BUFFER_LOCATION, src, last_copy_size);
+		lpc24xx_copy_buffer_to_flash (info, addr);
+	}
+
+	/* verify write */
+	memmap_value = GET32(MEMMAP);
+
+	disable_interrupts ();
+
+	PUT32(MEMMAP, 01);		/* we must make sure that initial 64
+				   bytes are taken from flash when we
+				   do the compare */
+
+	for (i = 0; i < cnt; i++) {
+		if (*dst_org != *src_org) {
+			printf ("Write failed. Byte %lX differs\n", i);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+		dst_org++;
+		src_org++;
+	}
+
+	PUT32(MEMMAP, memmap_value);
+	enable_interrupts ();
+
+	return ret;
+}
diff -upNr u-boot-orig/cpu/arm720t/lpc24xx/iap_entry.S u-boot/cpu/arm720t/lpc24xx/iap_entry.S
--- u-boot-orig/cpu/arm720t/lpc24xx/iap_entry.S	1970-01-01 01:00:00.000000000 +0100
+++ u-boot/cpu/arm720t/lpc24xx/iap_entry.S	2009-03-19 10:56:19.000000000 +0100
@@ -0,0 +1,7 @@
+IAP_ADDRESS:	.word	0x7FFFFFF1
+
+.globl iap_entry
+iap_entry:
+	ldr	r2, IAP_ADDRESS
+	bx	r2
+	mov	pc, lr
diff -upNr u-boot-orig/cpu/arm720t/lpc24xx/Makefile u-boot/cpu/arm720t/lpc24xx/Makefile
--- u-boot-orig/cpu/arm720t/lpc24xx/Makefile	1970-01-01 01:00:00.000000000 +0100
+++ u-boot/cpu/arm720t/lpc24xx/Makefile	2009-03-19 10:56:53.000000000 +0100
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	= flash.o
+SOBJS	= $(obj)iap_entry.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+# this MUST be compiled as thumb code!
+$(SOBJS):
+	$(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -upNr u-boot-orig/cpu/arm720t/serial.c u-boot/cpu/arm720t/serial.c
--- u-boot-orig/cpu/arm720t/serial.c	2009-03-18 00:42:12.000000000 +0100
+++ u-boot/cpu/arm720t/serial.c	2009-03-19 15:10:03.000000000 +0100
@@ -41,13 +41,27 @@ void serial_setbrg (void)
    unsigned int reg = 0;
switch (gd->baudrate) {
-	case   1200:	reg = 191;	break;
-	case   9600:	reg =  23;	break;
-	case  19200:	reg =  11;	break;
-	case  38400:	reg =   5;	break;
-	case  57600:	reg =   3;	break;
-	case 115200:	reg =   1;	break;
-	default:	hang ();	break;
+	case 1200:
+		reg = 191;
+		break;
+	case 9600:
+		reg = 23;
+		break;
+	case 19200:
+		reg = 11;
+		break;
+	case 38400:
+		reg = 5;
+		break;
+	case 57600:
+		reg = 3;
+		break;
+	case 115200:
+		reg = 1;
+		break;
+	default:
+		hang ();
+		break;
    }
/* init serial serial 1,2 */
@@ -60,7 +74,6 @@ void serial_setbrg (void)
    IO_UBRLCR2 = reg;
  }
-
  /*
   * Initialise the serial port with the given baudrate. The settings
   * are always 8 data bits, no parity, 1 stop bit, no start bits.
@@ -73,7 +86,6 @@ int serial_init (void)
    return (0);
  }
-
  /*
   * Output a single byte to the serial port.
   */
@@ -110,47 +122,92 @@ int serial_tstc (void)
   */
  int serial_getc (void)
  {
-	while (IO_SYSFLG1 & SYSFLG1_URXFE);
+	while (IO_SYSFLG1 & SYSFLG1_URXFE) ;
return IO_UARTDR1 & 0xff;
  }
-void
-serial_puts (const char *s)
+void serial_puts (const char *s)
  {
    while (*s) {
    	serial_putc (*s++);
    }
  }
-#elif defined(CONFIG_LPC2292)
+#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/hardware.h>
+void serial_putc (const char c)
+{
+	if (c == '\n') {
+		while ((GET8 (U0LSR) & (1 << 5)) == 0) ;	/* Wait for empty U0THR */
+		PUT8 (U0THR, '\r');
+	}
+
+	while ((GET8 (U0LSR) & (1 << 5)) == 0) ;	/* Wait for empty U0THR */
+	PUT8 (U0THR, c);
+}
+
+int serial_getc (void)
+{
+	while ((GET8 (U0LSR) & 1) == 0) ;
+	return GET8 (U0RBR);
+}
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+/* Test if there is a byte to read */
+int serial_tstc (void)
+{
+	return (GET8 (U0LSR) & 1);
+}
+
+#if defined(CONFIG_LPC2292)
+
  void serial_setbrg (void)
  {
    unsigned short divisor = 0;
switch (gd->baudrate) {
-	case   1200:	divisor = 3072;	break;
-	case   9600:	divisor =  384;	break;
-	case  19200:	divisor =  192;	break;
-	case  38400:	divisor =   96;	break;
-	case  57600:	divisor =   64;	break;
-	case 115200:	divisor =   32;	break;
-	default:	hang ();	break;
+	case 1200:
+		divisor = 3072;
+		break;
+	case 9600:
+		divisor = 384;
+		break;
+	case 19200:
+		divisor = 192;
+		break;
+	case 38400:
+		divisor = 96;
+		break;
+	case 57600:
+		divisor = 64;
+		break;
+	case 115200:
+		divisor = 32;
+		break;
+	default:
+		hang ();
+		break;
    }
/* init serial UART0 */
-	PUT8(U0LCR, 0);
-	PUT8(U0IER, 0);
-	PUT8(U0LCR, 0x80);	/* DLAB=1 */
-	PUT8(U0DLL, (unsigned char)(divisor & 0x00FF));
-	PUT8(U0DLM, (unsigned char)(divisor >> 8));
-	PUT8(U0LCR, 0x03);	/* 8N1, DLAB=0  */
-	PUT8(U0FCR, 1);		/* Enable RX and TX FIFOs */
+	PUT8 (U0LCR, 0);
+	PUT8 (U0IER, 0);
+	PUT8 (U0LCR, 0x80);	/* DLAB=1 */
+	PUT8 (U0DLL, (unsigned char)(divisor & 0x00FF));
+	PUT8 (U0DLM, (unsigned char)(divisor >> 8));
+	PUT8 (U0LCR, 0x03);	/* 8N1, DLAB=0  */
+	PUT8 (U0FCR, 1);	/* Enable RX and TX FIFOs */
  }
int serial_init (void)
@@ -159,44 +216,59 @@ int serial_init (void)
serial_setbrg ();
-	pinsel0 = GET32(PINSEL0);
+	pinsel0 = GET32 (PINSEL0);
    pinsel0 &= ~(0x00000003);
    pinsel0 |= 5;
-	PUT32(PINSEL0, pinsel0);
+	PUT32 (PINSEL0, pinsel0);
return (0);
  }
-void serial_putc (const char c)
-{
-	if (c == '\n')
-	{
-		while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */
-		PUT8(U0THR, '\r');
-	}
-
-	while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */
-	PUT8(U0THR, c);
-}
+#else
-int serial_getc (void)
+void serial_setbrg (void)
  {
-	while((GET8(U0LSR) & 1) == 0);
-	return GET8(U0RBR);
-}
+	unsigned short divisor;
-void
-serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
+	switch (gd->baudrate) {
+	case 1200:
+	case 9600:
+	case 19200:
+	case 38400:
+	case 57600:
+	case 115200:
+		divisor = CFG_SYS_CLK_FREQ / (gd->baudrate * 16);
+		break;
+	default:
+		hang ();
+		break;
    }
+	
+	/* init serial UART0 */
+	PUT8 (U0FCR, 0);	/* Disable RX and TX FIFOs */
+	PUT8 (U0LCR, 0);
+	PUT8 (U0IER, 0);
+	PUT8 (U0LCR, 0x80);	/* DLAB=1 */
+	PUT8 (U0DLL, (unsigned char)(divisor & 0x00FF));
+	PUT8 (U0DLM, (unsigned char)(divisor >> 8));
+	PUT8 (U0LCR, 0x03);	/* 8N1, DLAB=0  */
+	PUT8 (U0FCR, 0x7);	/* Enable RX and TX FIFOs */
  }
-/* Test if there is a byte to read */
-int serial_tstc (void)
+int serial_init (void)
  {
-	return (GET8(U0LSR) & 1);
+	unsigned long pinsel0;
+
+	/*enable uart #0 pins in GPIO (P0.2 = TxD0, P0.3 = RxD0) */
+	pinsel0 = GET32 (PINSEL0);
+	pinsel0 &= ~(0x000000f0);
+	pinsel0 |= 0x00000050;
+	PUT32 (PINSEL0, pinsel0);
+
+	serial_setbrg ();
+
+	return (0);
  }
#endif
+#endif /*defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) */
diff -upNr u-boot-orig/cpu/arm720t/start.S u-boot/cpu/arm720t/start.S
--- u-boot-orig/cpu/arm720t/start.S	2009-03-18 00:42:12.000000000 +0100
+++ u-boot/cpu/arm720t/start.S	2009-03-19 11:21:20.000000000 +0100
@@ -127,7 +127,7 @@ reset:
    bl	cpu_init_crit
  #endif
-#ifdef CONFIG_LPC2292
+#if	defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
    bl	lowlevel_init
  #endif
@@ -368,6 +368,10 @@ lock_loop:
    ldr	r0, VPBDIV_ADR
    mov	r1, #0x01	/* VPB clock is same as process clock */
    str	r1, [r0]
+#elif defined(CONFIG_LPC2468)
+    ldr r0, =0x40008000 /*0x40000000 is internal SRAM, 0x4000FFFF is end of SRAM*/
+    mov sp,r0
+    sub sl,sp,#0x2000
  #else
  #error No cpu_init_crit() defined for current CPU type
  #endif
@@ -383,7 +387,7 @@ lock_loop:
    str	r1, [r0]
  #endif
-#ifndef CONFIG_LPC2292
+#if	!defined(CONFIG_LPC2292) && !defined(CONFIG_LPC2468)
    mov	ip, lr
    /*
     * before relocating, we have to setup RAM timing
@@ -601,7 +605,7 @@ reset_cpu:
   * on external peripherals such as watchdog timers, etc. */
  #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
    /* No specific reset actions for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
+#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
    .align	5
  .globl reset_cpu
  reset_cpu:
diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h u-boot/include/asm-arm/arch-lpc24xx/hardware.h
--- u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h	1970-01-01 01:00:00.000000000 +0100
+++ u-boot/include/asm-arm/arch-lpc24xx/hardware.h	2009-03-18 09:31:46.000000000 +0100
@@ -0,0 +1,33 @@
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune curt@cucy.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if defined(CONFIG_LPC2468)
+#include <asm-arm/arch-lpc24xx/lpc24xx_registers.h>
+#else
+#error No hardware file defined for this configuration
+#endif
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h u-boot/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h
--- u-boot-orig/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h	1970-01-01 01:00:00.000000000 +0100
+++ u-boot/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h	2009-03-19 14:19:36.000000000 +0100
@@ -0,0 +1,1101 @@
+#ifndef __LPC24XX_REGISTERS_H
+#define __LPC24XX_REGISTERS_H
+
+#include <config.h>
+
+/* Macros for reading/writing registers */
+#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value))
+#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value))
+#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value))
+#define GET8(reg) (*(volatile unsigned char*)(reg))
+#define GET16(reg) (*(volatile unsigned short*)(reg))
+#define GET32(reg) (*(volatile unsigned int*)(reg))
+
+#define BFS32(reg,value) (*(volatile unsigned int*)(reg) |= (value))
+#define BFC32(reg, value) (*(volatile unsigned int*)(reg) &= (~value))
+
+/* Vectored Interrupt Controller (VIC) */
+#define VIC_BASE_ADDR	0xFFFFF000
+#define VICIRQStatus   VIC_BASE_ADDR + 0x000
+#define VICFIQStatus   VIC_BASE_ADDR + 0x004
+#define VICRawIntr     VIC_BASE_ADDR + 0x008
+#define VICIntSelect   VIC_BASE_ADDR + 0x00C
+#define VICIntEnable   VIC_BASE_ADDR + 0x010
+#define VICIntEnClr    VIC_BASE_ADDR + 0x014
+#define VICSoftInt     VIC_BASE_ADDR + 0x018
+#define VICSoftIntClr  VIC_BASE_ADDR + 0x01C
+#define VICProtection  VIC_BASE_ADDR + 0x020
+#define VICSWPrioMask  VIC_BASE_ADDR + 0x024
+
+#define VICVectAddr0   VIC_BASE_ADDR + 0x100
+#define VICVectAddr1   VIC_BASE_ADDR + 0x104
+#define VICVectAddr2   VIC_BASE_ADDR + 0x108
+#define VICVectAddr3   VIC_BASE_ADDR + 0x10C
+#define VICVectAddr4   VIC_BASE_ADDR + 0x110
+#define VICVectAddr5   VIC_BASE_ADDR + 0x114
+#define VICVectAddr6   VIC_BASE_ADDR + 0x118
+#define VICVectAddr7   VIC_BASE_ADDR + 0x11C
+#define VICVectAddr8   VIC_BASE_ADDR + 0x120
+#define VICVectAddr9   VIC_BASE_ADDR + 0x124
+#define VICVectAddr10  VIC_BASE_ADDR + 0x128
+#define VICVectAddr11  VIC_BASE_ADDR + 0x12C
+#define VICVectAddr12  VIC_BASE_ADDR + 0x130
+#define VICVectAddr13  VIC_BASE_ADDR + 0x134
+#define VICVectAddr14  VIC_BASE_ADDR + 0x138
+#define VICVectAddr15  VIC_BASE_ADDR + 0x13C
+#define VICVectAddr16  VIC_BASE_ADDR + 0x140
+#define VICVectAddr17  VIC_BASE_ADDR + 0x144
+#define VICVectAddr18  VIC_BASE_ADDR + 0x148
+#define VICVectAddr19  VIC_BASE_ADDR + 0x14C
+#define VICVectAddr20  VIC_BASE_ADDR + 0x150
+#define VICVectAddr21  VIC_BASE_ADDR + 0x154
+#define VICVectAddr22  VIC_BASE_ADDR + 0x158
+#define VICVectAddr23  VIC_BASE_ADDR + 0x15C
+#define VICVectAddr24  VIC_BASE_ADDR + 0x160
+#define VICVectAddr25  VIC_BASE_ADDR + 0x164
+#define VICVectAddr26  VIC_BASE_ADDR + 0x168
+#define VICVectAddr27  VIC_BASE_ADDR + 0x16C
+#define VICVectAddr28  VIC_BASE_ADDR + 0x170
+#define VICVectAddr29  VIC_BASE_ADDR + 0x174
+#define VICVectAddr30  VIC_BASE_ADDR + 0x178
+#define VICVectAddr31  VIC_BASE_ADDR + 0x17C
+
+/* The name convention below is from previous LPC2000 family MCUs, in LPC230x,
+these registers are known as "VICVectPriority(x)". */
+#define VICVectCntl0   VIC_BASE_ADDR + 0x200
+#define VICVectCntl1   VIC_BASE_ADDR + 0x204
+#define VICVectCntl2   VIC_BASE_ADDR + 0x208
+#define VICVectCntl3   VIC_BASE_ADDR + 0x20C
+#define VICVectCntl4   VIC_BASE_ADDR + 0x210
+#define VICVectCntl5   VIC_BASE_ADDR + 0x214
+#define VICVectCntl6   VIC_BASE_ADDR + 0x218
+#define VICVectCntl7   VIC_BASE_ADDR + 0x21C
+#define VICVectCntl8   VIC_BASE_ADDR + 0x220
+#define VICVectCntl9   VIC_BASE_ADDR + 0x224
+#define VICVectCntl10  VIC_BASE_ADDR + 0x228
+#define VICVectCntl11  VIC_BASE_ADDR + 0x22C
+#define VICVectCntl12  VIC_BASE_ADDR + 0x230
+#define VICVectCntl13  VIC_BASE_ADDR + 0x234
+#define VICVectCntl14  VIC_BASE_ADDR + 0x238
+#define VICVectCntl15  VIC_BASE_ADDR + 0x23C
+#define VICVectCntl16  VIC_BASE_ADDR + 0x240
+#define VICVectCntl17  VIC_BASE_ADDR + 0x244
+#define VICVectCntl18  VIC_BASE_ADDR + 0x248
+#define VICVectCntl19  VIC_BASE_ADDR + 0x24C
+#define VICVectCntl20  VIC_BASE_ADDR + 0x250
+#define VICVectCntl21  VIC_BASE_ADDR + 0x254
+#define VICVectCntl22  VIC_BASE_ADDR + 0x258
+#define VICVectCntl23  VIC_BASE_ADDR + 0x25C
+#define VICVectCntl24  VIC_BASE_ADDR + 0x260
+#define VICVectCntl25  VIC_BASE_ADDR + 0x264
+#define VICVectCntl26  VIC_BASE_ADDR + 0x268
+#define VICVectCntl27  VIC_BASE_ADDR + 0x26C
+#define VICVectCntl28  VIC_BASE_ADDR + 0x270
+#define VICVectCntl29  VIC_BASE_ADDR + 0x274
+#define VICVectCntl30  VIC_BASE_ADDR + 0x278
+#define VICVectCntl31  VIC_BASE_ADDR + 0x27C
+
+#define VICVectAddr    VIC_BASE_ADDR + 0xF00
+
+/* Pin Connect Block */
+#define PINSEL_BASE_ADDR	0xE002C000
+#define PINSEL0        PINSEL_BASE_ADDR + 0x00
+#define PINSEL1        PINSEL_BASE_ADDR + 0x04
+#define PINSEL2        PINSEL_BASE_ADDR + 0x08
+#define PINSEL3        PINSEL_BASE_ADDR + 0x0C
+#define PINSEL4        PINSEL_BASE_ADDR + 0x10
+#define PINSEL5        PINSEL_BASE_ADDR + 0x14
+#define PINSEL6        PINSEL_BASE_ADDR + 0x18
+#define PINSEL7        PINSEL_BASE_ADDR + 0x1C
+#define PINSEL8        PINSEL_BASE_ADDR + 0x20
+#define PINSEL9        PINSEL_BASE_ADDR + 0x24
+#define PINSEL10       PINSEL_BASE_ADDR + 0x28
+
+#define PINMODE0       PINSEL_BASE_ADDR + 0x40
+#define PINMODE1       PINSEL_BASE_ADDR + 0x44
+#define PINMODE2       PINSEL_BASE_ADDR + 0x48
+#define PINMODE3       PINSEL_BASE_ADDR + 0x4C
+#define PINMODE4       PINSEL_BASE_ADDR + 0x50
+#define PINMODE5       PINSEL_BASE_ADDR + 0x54
+#define PINMODE6       PINSEL_BASE_ADDR + 0x58
+#define PINMODE7       PINSEL_BASE_ADDR + 0x5C
+#define PINMODE8       PINSEL_BASE_ADDR + 0x60
+#define PINMODE9       PINSEL_BASE_ADDR + 0x64
+
+/* General Purpose Input/Output (GPIO) */
+#define GPIO_BASE_ADDR		0xE0028000
+#define IOPIN0         GPIO_BASE_ADDR + 0x00
+#define IOSET0         GPIO_BASE_ADDR + 0x04
+#define IODIR0         GPIO_BASE_ADDR + 0x08
+#define IOCLR0         GPIO_BASE_ADDR + 0x0C
+#define IOPIN1         GPIO_BASE_ADDR + 0x10
+#define IOSET1         GPIO_BASE_ADDR + 0x14
+#define IODIR1         GPIO_BASE_ADDR + 0x18
+#define IOCLR1         GPIO_BASE_ADDR + 0x1C
+
+/* GPIO Interrupt Registers */
+#define IO0_INT_EN_R    GPIO_BASE_ADDR + 0x90
+#define IO0_INT_EN_F    GPIO_BASE_ADDR + 0x94
+#define IO0_INT_STAT_R  GPIO_BASE_ADDR + 0x84
+#define IO0_INT_STAT_F  GPIO_BASE_ADDR + 0x88
+#define IO0_INT_CLR     GPIO_BASE_ADDR + 0x8C
+
+#define IO2_INT_EN_R    GPIO_BASE_ADDR + 0xB0
+#define IO2_INT_EN_F    GPIO_BASE_ADDR + 0xB4
+#define IO2_INT_STAT_R  GPIO_BASE_ADDR + 0xA4
+#define IO2_INT_STAT_F  GPIO_BASE_ADDR + 0xA8
+#define IO2_INT_CLR     GPIO_BASE_ADDR + 0xAC
+
+#define IO_INT_STAT     GPIO_BASE_ADDR + 0x80
+
+#define PARTCFG_BASE_ADDR		0x3FFF8000
+#define PARTCFG        PARTCFG_BASE_ADDR + 0x00
+
+/* Fast I/O setup */
+#define FIO_BASE_ADDR		0x3FFFC000
+#define FIO0DIR        FIO_BASE_ADDR + 0x00
+#define FIO0MASK       FIO_BASE_ADDR + 0x10
+#define FIO0PIN        FIO_BASE_ADDR + 0x14
+#define FIO0SET        FIO_BASE_ADDR + 0x18
+#define FIO0CLR        FIO_BASE_ADDR + 0x1C
+
+#define FIO1DIR        FIO_BASE_ADDR + 0x20
+#define FIO1MASK       FIO_BASE_ADDR + 0x30
+#define FIO1PIN        FIO_BASE_ADDR + 0x34
+#define FIO1SET        FIO_BASE_ADDR + 0x38
+#define FIO1CLR        FIO_BASE_ADDR + 0x3C
+
+#define FIO2DIR        FIO_BASE_ADDR + 0x40
+#define FIO2MASK       FIO_BASE_ADDR + 0x50
+#define FIO2PIN        FIO_BASE_ADDR + 0x54
+#define FIO2SET        FIO_BASE_ADDR + 0x58
+#define FIO2CLR        FIO_BASE_ADDR + 0x5C
+
+#define FIO3DIR        FIO_BASE_ADDR + 0x60
+#define FIO3MASK       FIO_BASE_ADDR + 0x70
+#define FIO3PIN        FIO_BASE_ADDR + 0x74
+#define FIO3SET        FIO_BASE_ADDR + 0x78
+#define FIO3CLR        FIO_BASE_ADDR + 0x7C
+
+#define FIO4DIR        FIO_BASE_ADDR + 0x80
+#define FIO4MASK       FIO_BASE_ADDR + 0x90
+#define FIO4PIN        FIO_BASE_ADDR + 0x94
+#define FIO4SET        FIO_BASE_ADDR + 0x98
+#define FIO4CLR        FIO_BASE_ADDR + 0x9C
+
+/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
+#define FIO0DIR0       FIO_BASE_ADDR + 0x01
+#define FIO1DIR0       FIO_BASE_ADDR + 0x21
+#define FIO2DIR0       FIO_BASE_ADDR + 0x41
+#define FIO3DIR0       FIO_BASE_ADDR + 0x61
+#define FIO4DIR0       FIO_BASE_ADDR + 0x81
+
+#define FIO0DIR1       FIO_BASE_ADDR + 0x02
+#define FIO1DIR1       FIO_BASE_ADDR + 0x22
+#define FIO2DIR1       FIO_BASE_ADDR + 0x42
+#define FIO3DIR1       FIO_BASE_ADDR + 0x62
+#define FIO4DIR1       FIO_BASE_ADDR + 0x82
+
+#define FIO0DIR2       FIO_BASE_ADDR + 0x03
+#define FIO1DIR2       FIO_BASE_ADDR + 0x23
+#define FIO2DIR2       FIO_BASE_ADDR + 0x43
+#define FIO3DIR2       FIO_BASE_ADDR + 0x63
+#define FIO4DIR2       FIO_BASE_ADDR + 0x83
+
+#define FIO0DIR3       FIO_BASE_ADDR + 0x04
+#define FIO1DIR3       FIO_BASE_ADDR + 0x24
+#define FIO2DIR3       FIO_BASE_ADDR + 0x44
+#define FIO3DIR3       FIO_BASE_ADDR + 0x64
+#define FIO4DIR3       FIO_BASE_ADDR + 0x84
+
+#define FIO0DIRL       FIO_BASE_ADDR + 0x00
+#define FIO1DIRL       FIO_BASE_ADDR + 0x20
+#define FIO2DIRL       FIO_BASE_ADDR + 0x40
+#define FIO3DIRL       FIO_BASE_ADDR + 0x60
+#define FIO4DIRL       FIO_BASE_ADDR + 0x80
+
+#define FIO0DIRU       FIO_BASE_ADDR + 0x02
+#define FIO1DIRU       FIO_BASE_ADDR + 0x22
+#define FIO2DIRU       FIO_BASE_ADDR + 0x42
+#define FIO3DIRU       FIO_BASE_ADDR + 0x62
+#define FIO4DIRU       FIO_BASE_ADDR + 0x82
+
+#define FIO0MASK0      FIO_BASE_ADDR + 0x10
+#define FIO1MASK0      FIO_BASE_ADDR + 0x30
+#define FIO2MASK0      FIO_BASE_ADDR + 0x50
+#define FIO3MASK0      FIO_BASE_ADDR + 0x70
+#define FIO4MASK0      FIO_BASE_ADDR + 0x90
+
+#define FIO0MASK1      FIO_BASE_ADDR + 0x11
+#define FIO1MASK1      FIO_BASE_ADDR + 0x21
+#define FIO2MASK1      FIO_BASE_ADDR + 0x51
+#define FIO3MASK1      FIO_BASE_ADDR + 0x71
+#define FIO4MASK1      FIO_BASE_ADDR + 0x91
+
+#define FIO0MASK2      FIO_BASE_ADDR + 0x12
+#define FIO1MASK2      FIO_BASE_ADDR + 0x32
+#define FIO2MASK2      FIO_BASE_ADDR + 0x52
+#define FIO3MASK2      FIO_BASE_ADDR + 0x72
+#define FIO4MASK2      FIO_BASE_ADDR + 0x92
+
+#define FIO0MASK3      FIO_BASE_ADDR + 0x13
+#define FIO1MASK3      FIO_BASE_ADDR + 0x33
+#define FIO2MASK3      FIO_BASE_ADDR + 0x53
+#define FIO3MASK3      FIO_BASE_ADDR + 0x73
+#define FIO4MASK3      FIO_BASE_ADDR + 0x93
+
+#define FIO0MASKL      FIO_BASE_ADDR + 0x10
+#define FIO1MASKL      FIO_BASE_ADDR + 0x30
+#define FIO2MASKL      FIO_BASE_ADDR + 0x50
+#define FIO3MASKL      FIO_BASE_ADDR + 0x70
+#define FIO4MASKL      FIO_BASE_ADDR + 0x90
+
+#define FIO0MASKU      FIO_BASE_ADDR + 0x12
+#define FIO1MASKU      FIO_BASE_ADDR + 0x32
+#define FIO2MASKU      FIO_BASE_ADDR + 0x52
+#define FIO3MASKU      FIO_BASE_ADDR + 0x72
+#define FIO4MASKU      FIO_BASE_ADDR + 0x92
+
+#define FIO0PIN0       FIO_BASE_ADDR + 0x14
+#define FIO1PIN0       FIO_BASE_ADDR + 0x34
+#define FIO2PIN0       FIO_BASE_ADDR + 0x54
+#define FIO3PIN0       FIO_BASE_ADDR + 0x74
+#define FIO4PIN0       FIO_BASE_ADDR + 0x94
+
+#define FIO0PIN1       FIO_BASE_ADDR + 0x15
+#define FIO1PIN1       FIO_BASE_ADDR + 0x25
+#define FIO2PIN1       FIO_BASE_ADDR + 0x55
+#define FIO3PIN1       FIO_BASE_ADDR + 0x75
+#define FIO4PIN1       FIO_BASE_ADDR + 0x95
+
+#define FIO0PIN2       FIO_BASE_ADDR + 0x16
+#define FIO1PIN2       FIO_BASE_ADDR + 0x36
+#define FIO2PIN2       FIO_BASE_ADDR + 0x56
+#define FIO3PIN2       FIO_BASE_ADDR + 0x76
+#define FIO4PIN2       FIO_BASE_ADDR + 0x96
+
+#define FIO0PIN3       FIO_BASE_ADDR + 0x17
+#define FIO1PIN3       FIO_BASE_ADDR + 0x37
+#define FIO2PIN3       FIO_BASE_ADDR + 0x57
+#define FIO3PIN3       FIO_BASE_ADDR + 0x77
+#define FIO4PIN3       FIO_BASE_ADDR + 0x97
+
+#define FIO0PINL       FIO_BASE_ADDR + 0x14
+#define FIO1PINL       FIO_BASE_ADDR + 0x34
+#define FIO2PINL       FIO_BASE_ADDR + 0x54
+#define FIO3PINL       FIO_BASE_ADDR + 0x74
+#define FIO4PINL       FIO_BASE_ADDR + 0x94
+
+#define FIO0PINU       FIO_BASE_ADDR + 0x16
+#define FIO1PINU       FIO_BASE_ADDR + 0x36
+#define FIO2PINU       FIO_BASE_ADDR + 0x56
+#define FIO3PINU       FIO_BASE_ADDR + 0x76
+#define FIO4PINU       FIO_BASE_ADDR + 0x96
+
+#define FIO0SET0       FIO_BASE_ADDR + 0x18
+#define FIO1SET0       FIO_BASE_ADDR + 0x38
+#define FIO2SET0       FIO_BASE_ADDR + 0x58
+#define FIO3SET0       FIO_BASE_ADDR + 0x78
+#define FIO4SET0       FIO_BASE_ADDR + 0x98
+
+#define FIO0SET1       FIO_BASE_ADDR + 0x19
+#define FIO1SET1       FIO_BASE_ADDR + 0x29
+#define FIO2SET1       FIO_BASE_ADDR + 0x59
+#define FIO3SET1       FIO_BASE_ADDR + 0x79
+#define FIO4SET1       FIO_BASE_ADDR + 0x99
+
+#define FIO0SET2       FIO_BASE_ADDR + 0x1A
+#define FIO1SET2       FIO_BASE_ADDR + 0x3A
+#define FIO2SET2       FIO_BASE_ADDR + 0x5A
+#define FIO3SET2       FIO_BASE_ADDR + 0x7A
+#define FIO4SET2       FIO_BASE_ADDR + 0x9A
+
+#define FIO0SET3       FIO_BASE_ADDR + 0x1B
+#define FIO1SET3       FIO_BASE_ADDR + 0x3B
+#define FIO2SET3       FIO_BASE_ADDR + 0x5B
+#define FIO3SET3       FIO_BASE_ADDR + 0x7B
+#define FIO4SET3       FIO_BASE_ADDR + 0x9B
+
+#define FIO0SETL       FIO_BASE_ADDR + 0x18
+#define FIO1SETL       FIO_BASE_ADDR + 0x38
+#define FIO2SETL       FIO_BASE_ADDR + 0x58
+#define FIO3SETL       FIO_BASE_ADDR + 0x78
+#define FIO4SETL       FIO_BASE_ADDR + 0x98
+
+#define FIO0SETU       FIO_BASE_ADDR + 0x1A
+#define FIO1SETU       FIO_BASE_ADDR + 0x3A
+#define FIO2SETU       FIO_BASE_ADDR + 0x5A
+#define FIO3SETU       FIO_BASE_ADDR + 0x7A
+#define FIO4SETU       FIO_BASE_ADDR + 0x9A
+
+#define FIO0CLR0       FIO_BASE_ADDR + 0x1C
+#define FIO1CLR0       FIO_BASE_ADDR + 0x3C
+#define FIO2CLR0       FIO_BASE_ADDR + 0x5C
+#define FIO3CLR0       FIO_BASE_ADDR + 0x7C
+#define FIO4CLR0       FIO_BASE_ADDR + 0x9C
+
+#define FIO0CLR1       FIO_BASE_ADDR + 0x1D
+#define FIO1CLR1       FIO_BASE_ADDR + 0x2D
+#define FIO2CLR1       FIO_BASE_ADDR + 0x5D
+#define FIO3CLR1       FIO_BASE_ADDR + 0x7D
+#define FIO4CLR1       FIO_BASE_ADDR + 0x9D
+
+#define FIO0CLR2       FIO_BASE_ADDR + 0x1E
+#define FIO1CLR2       FIO_BASE_ADDR + 0x3E
+#define FIO2CLR2       FIO_BASE_ADDR + 0x5E
+#define FIO3CLR2       FIO_BASE_ADDR + 0x7E
+#define FIO4CLR2       FIO_BASE_ADDR + 0x9E
+
+#define FIO0CLR3       FIO_BASE_ADDR + 0x1F
+#define FIO1CLR3       FIO_BASE_ADDR + 0x3F
+#define FIO2CLR3       FIO_BASE_ADDR + 0x5F
+#define FIO3CLR3       FIO_BASE_ADDR + 0x7F
+#define FIO4CLR3       FIO_BASE_ADDR + 0x9F
+
+#define FIO0CLRL       FIO_BASE_ADDR + 0x1C
+#define FIO1CLRL       FIO_BASE_ADDR + 0x3C
+#define FIO2CLRL       FIO_BASE_ADDR + 0x5C
+#define FIO3CLRL       FIO_BASE_ADDR + 0x7C
+#define FIO4CLRL       FIO_BASE_ADDR + 0x9C
+
+#define FIO0CLRU       FIO_BASE_ADDR + 0x1E
+#define FIO1CLRU       FIO_BASE_ADDR + 0x3E
+#define FIO2CLRU       FIO_BASE_ADDR + 0x5E
+#define FIO3CLRU       FIO_BASE_ADDR + 0x7E
+#define FIO4CLRU       FIO_BASE_ADDR + 0x9E
+
+/* System Control Block(SCB) modules include Memory Accelerator Module,
+Phase Locked Loop, VPB divider, Power Control, External Interrupt,
+Reset, and Code Security/Debugging */
+#define SCB_BASE_ADDR	0xE01FC000
+
+/* Memory Accelerator Module (MAM) */
+#define MAMCR          SCB_BASE_ADDR + 0x000
+#define MAMTIM         SCB_BASE_ADDR + 0x004
+#define MEMMAP         SCB_BASE_ADDR + 0x040
+
+/* Phase Locked Loop (PLL) */
+#define PLLCON         SCB_BASE_ADDR + 0x080
+#define PLLCFG         SCB_BASE_ADDR + 0x084
+#define PLLSTAT        SCB_BASE_ADDR + 0x088
+#define PLLFEED        SCB_BASE_ADDR + 0x08C
+
+/* Power Control */
+#define PCON           SCB_BASE_ADDR + 0x0C0
+#define PCONP          SCB_BASE_ADDR + 0x0C4
+
+/* Clock Divider */
+// #define APBDIV         SCB_BASE_ADDR + 0x100
+#define CCLKCFG        SCB_BASE_ADDR + 0x104
+#define USBCLKCFG      SCB_BASE_ADDR + 0x108
+#define CLKSRCSEL      SCB_BASE_ADDR + 0x10C
+#define PCLKSEL0       SCB_BASE_ADDR + 0x1A8
+#define PCLKSEL1       SCB_BASE_ADDR + 0x1AC
+
+/* External Interrupts */
+#define EXTINT         SCB_BASE_ADDR + 0x140
+#define INTWAKE        SCB_BASE_ADDR + 0x144
+#define EXTMODE        SCB_BASE_ADDR + 0x148
+#define EXTPOLAR       SCB_BASE_ADDR + 0x14C
+
+/* Reset, reset source identification */
+#define RSIR           SCB_BASE_ADDR + 0x180
+
+/* RSID, code security protection */
+#define CSPR           SCB_BASE_ADDR + 0x184
+
+/* AHB configuration */
+#define AHBCFG1        SCB_BASE_ADDR + 0x188
+#define AHBCFG2        SCB_BASE_ADDR + 0x18C
+
+/* System Controls and Status */
+#define SCS            SCB_BASE_ADDR + 0x1A0
+
+/* External Memory Controller (EMC) */
+#define EMC_BASE_ADDR		0xFFE08000
+#define EMC_CTRL       EMC_BASE_ADDR + 0x000
+#define EMC_STAT       EMC_BASE_ADDR + 0x004
+#define EMC_CONFIG     EMC_BASE_ADDR + 0x008
+
+/* Dynamic RAM access registers */
+#define EMC_DYN_CTRL     EMC_BASE_ADDR + 0x020
+#define EMC_DYN_RFSH     EMC_BASE_ADDR + 0x024
+#define EMC_DYN_RD_CFG   EMC_BASE_ADDR + 0x028
+#define EMC_DYN_RP       EMC_BASE_ADDR + 0x030
+#define EMC_DYN_RAS      EMC_BASE_ADDR + 0x034
+#define EMC_DYN_SREX     EMC_BASE_ADDR + 0x038
+#define EMC_DYN_APR      EMC_BASE_ADDR + 0x03C
+#define EMC_DYN_DAL      EMC_BASE_ADDR + 0x040
+#define EMC_DYN_WR       EMC_BASE_ADDR + 0x044
+#define EMC_DYN_RC       EMC_BASE_ADDR + 0x048
+#define EMC_DYN_RFC      EMC_BASE_ADDR + 0x04C
+#define EMC_DYN_XSR      EMC_BASE_ADDR + 0x050
+#define EMC_DYN_RRD      EMC_BASE_ADDR + 0x054
+#define EMC_DYN_MRD      EMC_BASE_ADDR + 0x058
+
+#define EMC_DYN_CFG0     EMC_BASE_ADDR + 0x100
+#define EMC_DYN_RASCAS0  EMC_BASE_ADDR + 0x104
+#define EMC_DYN_CFG1     EMC_BASE_ADDR + 0x140
+#define EMC_DYN_RASCAS1  EMC_BASE_ADDR + 0x144
+#define EMC_DYN_CFG2     EMC_BASE_ADDR + 0x160
+#define EMC_DYN_RASCAS2  EMC_BASE_ADDR + 0x164
+#define EMC_DYN_CFG3     EMC_BASE_ADDR + 0x180
+#define EMC_DYN_RASCAS3  EMC_BASE_ADDR + 0x184
+
+/* static RAM access registers */
+#define EMC_STA_CFG0      EMC_BASE_ADDR + 0x200
+#define EMC_STA_WAITWEN0  EMC_BASE_ADDR + 0x204
+#define EMC_STA_WAITOEN0  EMC_BASE_ADDR + 0x208
+#define EMC_STA_WAITRD0   EMC_BASE_ADDR + 0x20C
+#define EMC_STA_WAITPAGE0 EMC_BASE_ADDR + 0x210
+#define EMC_STA_WAITWR0   EMC_BASE_ADDR + 0x214
+#define EMC_STA_WAITTURN0 EMC_BASE_ADDR + 0x218
+
+#define EMC_STA_CFG1      EMC_BASE_ADDR + 0x220
+#define EMC_STA_WAITWEN1  EMC_BASE_ADDR + 0x224
+#define EMC_STA_WAITOEN1  EMC_BASE_ADDR + 0x228
+#define EMC_STA_WAITRD1   EMC_BASE_ADDR + 0x22C
+#define EMC_STA_WAITPAGE1 EMC_BASE_ADDR + 0x230
+#define EMC_STA_WAITWR1   EMC_BASE_ADDR + 0x234
+#define EMC_STA_WAITTURN1 EMC_BASE_ADDR + 0x238
+
+#define EMC_STA_CFG2      EMC_BASE_ADDR + 0x240
+#define EMC_STA_WAITWEN2  EMC_BASE_ADDR + 0x244
+#define EMC_STA_WAITOEN2  EMC_BASE_ADDR + 0x248
+#define EMC_STA_WAITRD2   EMC_BASE_ADDR + 0x24C
+#define EMC_STA_WAITPAGE2 EMC_BASE_ADDR + 0x250
+#define EMC_STA_WAITWR2   EMC_BASE_ADDR + 0x254
+#define EMC_STA_WAITTURN2 EMC_BASE_ADDR + 0x258
+
+#define EMC_STA_CFG3      EMC_BASE_ADDR + 0x260
+#define EMC_STA_WAITWEN3  EMC_BASE_ADDR + 0x264
+#define EMC_STA_WAITOEN3  EMC_BASE_ADDR + 0x268
+#define EMC_STA_WAITRD3   EMC_BASE_ADDR + 0x26C
+#define EMC_STA_WAITPAGE3 EMC_BASE_ADDR + 0x270
+#define EMC_STA_WAITWR3   EMC_BASE_ADDR + 0x274
+#define EMC_STA_WAITTURN3 EMC_BASE_ADDR + 0x278
+
+#define EMC_STA_EXT_WAIT  EMC_BASE_ADDR + 0x880
+
+/* Timer 0 */
+#define TMR0_BASE_ADDR		0xE0004000
+#define T0IR           TMR0_BASE_ADDR + 0x00
+#define T0TCR          TMR0_BASE_ADDR + 0x04
+#define T0TC           TMR0_BASE_ADDR + 0x08
+#define T0PR           TMR0_BASE_ADDR + 0x0C
+#define T0PC           TMR0_BASE_ADDR + 0x10
+#define T0MCR          TMR0_BASE_ADDR + 0x14
+#define T0MR0          TMR0_BASE_ADDR + 0x18
+#define T0MR1          TMR0_BASE_ADDR + 0x1C
+#define T0MR2          TMR0_BASE_ADDR + 0x20
+#define T0MR3          TMR0_BASE_ADDR + 0x24
+#define T0CCR          TMR0_BASE_ADDR + 0x28
+#define T0CR0          TMR0_BASE_ADDR + 0x2C
+#define T0CR1          TMR0_BASE_ADDR + 0x30
+#define T0CR2          TMR0_BASE_ADDR + 0x34
+#define T0CR3          TMR0_BASE_ADDR + 0x38
+#define T0EMR          TMR0_BASE_ADDR + 0x3C
+#define T0CTCR         TMR0_BASE_ADDR + 0x70
+
+/* Timer 1 */
+#define TMR1_BASE_ADDR		0xE0008000
+#define T1IR           TMR1_BASE_ADDR + 0x00
+#define T1TCR          TMR1_BASE_ADDR + 0x04
+#define T1TC           TMR1_BASE_ADDR + 0x08
+#define T1PR           TMR1_BASE_ADDR + 0x0C
+#define T1PC           TMR1_BASE_ADDR + 0x10
+#define T1MCR          TMR1_BASE_ADDR + 0x14
+#define T1MR0          TMR1_BASE_ADDR + 0x18
+#define T1MR1          TMR1_BASE_ADDR + 0x1C
+#define T1MR2          TMR1_BASE_ADDR + 0x20
+#define T1MR3          TMR1_BASE_ADDR + 0x24
+#define T1CCR          TMR1_BASE_ADDR + 0x28
+#define T1CR0          TMR1_BASE_ADDR + 0x2C
+#define T1CR1          TMR1_BASE_ADDR + 0x30
+#define T1CR2          TMR1_BASE_ADDR + 0x34
+#define T1CR3          TMR1_BASE_ADDR + 0x38
+#define T1EMR          TMR1_BASE_ADDR + 0x3C
+#define T1CTCR         TMR1_BASE_ADDR + 0x70
+
+/* Timer 2 */
+#define TMR2_BASE_ADDR		0xE0070000
+#define T2IR           TMR2_BASE_ADDR + 0x00
+#define T2TCR          TMR2_BASE_ADDR + 0x04
+#define T2TC           TMR2_BASE_ADDR + 0x08
+#define T2PR           TMR2_BASE_ADDR + 0x0C
+#define T2PC           TMR2_BASE_ADDR + 0x10
+#define T2MCR          TMR2_BASE_ADDR + 0x14
+#define T2MR0          TMR2_BASE_ADDR + 0x18
+#define T2MR1          TMR2_BASE_ADDR + 0x1C
+#define T2MR2          TMR2_BASE_ADDR + 0x20
+#define T2MR3          TMR2_BASE_ADDR + 0x24
+#define T2CCR          TMR2_BASE_ADDR + 0x28
+#define T2CR0          TMR2_BASE_ADDR + 0x2C
+#define T2CR1          TMR2_BASE_ADDR + 0x30
+#define T2CR2          TMR2_BASE_ADDR + 0x34
+#define T2CR3          TMR2_BASE_ADDR + 0x38
+#define T2EMR          TMR2_BASE_ADDR + 0x3C
+#define T2CTCR         TMR2_BASE_ADDR + 0x70
+
+/* Timer 3 */
+#define TMR3_BASE_ADDR		0xE0074000
+#define T3IR           TMR3_BASE_ADDR + 0x00
+#define T3TCR          TMR3_BASE_ADDR + 0x04
+#define T3TC           TMR3_BASE_ADDR + 0x08
+#define T3PR           TMR3_BASE_ADDR + 0x0C
+#define T3PC           TMR3_BASE_ADDR + 0x10
+#define T3MCR          TMR3_BASE_ADDR + 0x14
+#define T3MR0          TMR3_BASE_ADDR + 0x18
+#define T3MR1          TMR3_BASE_ADDR + 0x1C
+#define T3MR2          TMR3_BASE_ADDR + 0x20
+#define T3MR3          TMR3_BASE_ADDR + 0x24
+#define T3CCR          TMR3_BASE_ADDR + 0x28
+#define T3CR0          TMR3_BASE_ADDR + 0x2C
+#define T3CR1          TMR3_BASE_ADDR + 0x30
+#define T3CR2          TMR3_BASE_ADDR + 0x34
+#define T3CR3          TMR3_BASE_ADDR + 0x38
+#define T3EMR          TMR3_BASE_ADDR + 0x3C
+#define T3CTCR         TMR3_BASE_ADDR + 0x70
+
+/* Pulse Width Modulator (PWM) */
+#define PWM0_BASE_ADDR		0xE0014000
+#define PWM0IR          PWM0_BASE_ADDR + 0x00
+#define PWM0TCR         PWM0_BASE_ADDR + 0x04
+#define PWM0TC          PWM0_BASE_ADDR + 0x08
+#define PWM0PR          PWM0_BASE_ADDR + 0x0C
+#define PWM0PC          PWM0_BASE_ADDR + 0x10
+#define PWM0MCR         PWM0_BASE_ADDR + 0x14
+#define PWM0MR0         PWM0_BASE_ADDR + 0x18
+#define PWM0MR1         PWM0_BASE_ADDR + 0x1C
+#define PWM0MR2         PWM0_BASE_ADDR + 0x20
+#define PWM0MR3         PWM0_BASE_ADDR + 0x24
+#define PWM0CCR         PWM0_BASE_ADDR + 0x28
+#define PWM0CR0         PWM0_BASE_ADDR + 0x2C
+#define PWM0CR1         PWM0_BASE_ADDR + 0x30
+#define PWM0CR2         PWM0_BASE_ADDR + 0x34
+#define PWM0CR3         PWM0_BASE_ADDR + 0x38
+#define PWM0EMR         PWM0_BASE_ADDR + 0x3C
+#define PWM0MR4         PWM0_BASE_ADDR + 0x40
+#define PWM0MR5         PWM0_BASE_ADDR + 0x44
+#define PWM0MR6         PWM0_BASE_ADDR + 0x48
+#define PWM0PCR         PWM0_BASE_ADDR + 0x4C
+#define PWM0LER         PWM0_BASE_ADDR + 0x50
+#define PWM0CTCR        PWM0_BASE_ADDR + 0x70
+
+#define PWM1_BASE_ADDR		0xE0018000
+#define PWM1IR          PWM1_BASE_ADDR + 0x00
+#define PWM1TCR         PWM1_BASE_ADDR + 0x04
+#define PWM1TC          PWM1_BASE_ADDR + 0x08
+#define PWM1PR          PWM1_BASE_ADDR + 0x0C
+#define PWM1PC          PWM1_BASE_ADDR + 0x10
+#define PWM1MCR         PWM1_BASE_ADDR + 0x14
+#define PWM1MR0         PWM1_BASE_ADDR + 0x18
+#define PWM1MR1         PWM1_BASE_ADDR + 0x1C
+#define PWM1MR2         PWM1_BASE_ADDR + 0x20
+#define PWM1MR3         PWM1_BASE_ADDR + 0x24
+#define PWM1CCR         PWM1_BASE_ADDR + 0x28
+#define PWM1CR0         PWM1_BASE_ADDR + 0x2C
+#define PWM1CR1         PWM1_BASE_ADDR + 0x30
+#define PWM1CR2         PWM1_BASE_ADDR + 0x34
+#define PWM1CR3         PWM1_BASE_ADDR + 0x38
+#define PWM1EMR         PWM1_BASE_ADDR + 0x3C
+#define PWM1MR4         PWM1_BASE_ADDR + 0x40
+#define PWM1MR5         PWM1_BASE_ADDR + 0x44
+#define PWM1MR6         PWM1_BASE_ADDR + 0x48
+#define PWM1PCR         PWM1_BASE_ADDR + 0x4C
+#define PWM1LER         PWM1_BASE_ADDR + 0x50
+#define PWM1CTCR        PWM1_BASE_ADDR + 0x70
+
+/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
+#define UART0_BASE_ADDR		0xE000C000
+#define U0RBR          UART0_BASE_ADDR + 0x00
+#define U0THR          UART0_BASE_ADDR + 0x00
+#define U0DLL          UART0_BASE_ADDR + 0x00
+#define U0DLM          UART0_BASE_ADDR + 0x04
+#define U0IER          UART0_BASE_ADDR + 0x04
+#define U0IIR          UART0_BASE_ADDR + 0x08
+#define U0FCR          UART0_BASE_ADDR + 0x08
+#define U0LCR          UART0_BASE_ADDR + 0x0C
+#define U0LSR          UART0_BASE_ADDR + 0x14
+#define U0SCR          UART0_BASE_ADDR + 0x1C
+#define U0ACR          UART0_BASE_ADDR + 0x20
+#define U0FDR          UART0_BASE_ADDR + 0x28
+#define U0TER          UART0_BASE_ADDR + 0x30
+
+/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
+#define UART1_BASE_ADDR		0xE0010000
+#define U1RBR          UART1_BASE_ADDR + 0x00
+#define U1THR          UART1_BASE_ADDR + 0x00
+#define U1DLL          UART1_BASE_ADDR + 0x00
+#define U1DLM          UART1_BASE_ADDR + 0x04
+#define U1IER          UART1_BASE_ADDR + 0x04
+#define U1IIR          UART1_BASE_ADDR + 0x08
+#define U1FCR          UART1_BASE_ADDR + 0x08
+#define U1LCR          UART1_BASE_ADDR + 0x0C
+#define U1MCR          UART1_BASE_ADDR + 0x10
+#define U1LSR          UART1_BASE_ADDR + 0x14
+#define U1MSR          UART1_BASE_ADDR + 0x18
+#define U1SCR          UART1_BASE_ADDR + 0x1C
+#define U1ACR          UART1_BASE_ADDR + 0x20
+#define U1FDR          UART1_BASE_ADDR + 0x28
+#define U1TER          UART1_BASE_ADDR + 0x30
+
+/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
+#define UART2_BASE_ADDR		0xE0078000
+#define U2RBR          UART2_BASE_ADDR + 0x00
+#define U2THR          UART2_BASE_ADDR + 0x00
+#define U2DLL          UART2_BASE_ADDR + 0x00
+#define U2DLM          UART2_BASE_ADDR + 0x04
+#define U2IER          UART2_BASE_ADDR + 0x04
+#define U2IIR          UART2_BASE_ADDR + 0x08
+#define U2FCR          UART2_BASE_ADDR + 0x08
+#define U2LCR          UART2_BASE_ADDR + 0x0C
+#define U2LSR          UART2_BASE_ADDR + 0x14
+#define U2SCR          UART2_BASE_ADDR + 0x1C
+#define U2ACR          UART2_BASE_ADDR + 0x20
+#define U2ICR          UART2_BASE_ADDR + 0x24
+#define U2FDR          UART2_BASE_ADDR + 0x28
+#define U2TER          UART2_BASE_ADDR + 0x30
+
+/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
+#define UART3_BASE_ADDR		0xE007C000
+#define U3RBR          UART3_BASE_ADDR + 0x00
+#define U3THR          UART3_BASE_ADDR + 0x00
+#define U3DLL          UART3_BASE_ADDR + 0x00
+#define U3DLM          UART3_BASE_ADDR + 0x04
+#define U3IER          UART3_BASE_ADDR + 0x04
+#define U3IIR          UART3_BASE_ADDR + 0x08
+#define U3FCR          UART3_BASE_ADDR + 0x08
+#define U3LCR          UART3_BASE_ADDR + 0x0C
+#define U3LSR          UART3_BASE_ADDR + 0x14
+#define U3SCR          UART3_BASE_ADDR + 0x1C
+#define U3ACR          UART3_BASE_ADDR + 0x20
+#define U3ICR          UART3_BASE_ADDR + 0x24
+#define U3FDR          UART3_BASE_ADDR + 0x28
+#define U3TER          UART3_BASE_ADDR + 0x30
+
+/* I2C Interface 0 */
+#define I2C0_BASE_ADDR		0xE001C000
+#define I20CONSET      I2C0_BASE_ADDR + 0x00
+#define I20STAT        I2C0_BASE_ADDR + 0x04
+#define I20DAT         I2C0_BASE_ADDR + 0x08
+#define I20ADR         I2C0_BASE_ADDR + 0x0C
+#define I20SCLH        I2C0_BASE_ADDR + 0x10
+#define I20SCLL        I2C0_BASE_ADDR + 0x14
+#define I20CONCLR      I2C0_BASE_ADDR + 0x18
+
+/* I2C Interface 1 */
+#define I2C1_BASE_ADDR		0xE005C000
+#define I21CONSET      I2C1_BASE_ADDR + 0x00
+#define I21STAT        I2C1_BASE_ADDR + 0x04
+#define I21DAT         I2C1_BASE_ADDR + 0x08
+#define I21ADR         I2C1_BASE_ADDR + 0x0C
+#define I21SCLH        I2C1_BASE_ADDR + 0x10
+#define I21SCLL        I2C1_BASE_ADDR + 0x14
+#define I21CONCLR      I2C1_BASE_ADDR + 0x18
+
+/* I2C Interface 2 */
+#define I2C2_BASE_ADDR		0xE0080000
+#define I22CONSET      I2C2_BASE_ADDR + 0x00
+#define I22STAT        I2C2_BASE_ADDR + 0x04
+#define I22DAT         I2C2_BASE_ADDR + 0x08
+#define I22ADR         I2C2_BASE_ADDR + 0x0C
+#define I22SCLH        I2C2_BASE_ADDR + 0x10
+#define I22SCLL        I2C2_BASE_ADDR + 0x14
+#define I22CONCLR      I2C2_BASE_ADDR + 0x18
+
+/* SPI0 (Serial Peripheral Interface 0) */
+#define SPI0_BASE_ADDR		0xE0020000
+#define S0SPCR         SPI0_BASE_ADDR + 0x00
+#define S0SPSR         SPI0_BASE_ADDR + 0x04
+#define S0SPDR         SPI0_BASE_ADDR + 0x08
+#define S0SPCCR        SPI0_BASE_ADDR + 0x0C
+#define S0SPINT        SPI0_BASE_ADDR + 0x1C
+
+/* SSP0 Controller */
+#define SSP0_BASE_ADDR		0xE0068000
+#define SSP0CR0        SSP0_BASE_ADDR + 0x00
+#define SSP0CR1        SSP0_BASE_ADDR + 0x04
+#define SSP0DR         SSP0_BASE_ADDR + 0x08
+#define SSP0SR         SSP0_BASE_ADDR + 0x0C
+#define SSP0CPSR       SSP0_BASE_ADDR + 0x10
+#define SSP0IMSC       SSP0_BASE_ADDR + 0x14
+#define SSP0RIS        SSP0_BASE_ADDR + 0x18
+#define SSP0MIS        SSP0_BASE_ADDR + 0x1C
+#define SSP0ICR        SSP0_BASE_ADDR + 0x20
+#define SSP0DMACR      SSP0_BASE_ADDR + 0x24
+
+/* SSP1 Controller */
+#define SSP1_BASE_ADDR		0xE0030000
+#define SSP1CR0        SSP1_BASE_ADDR + 0x00
+#define SSP1CR1        SSP1_BASE_ADDR + 0x04
+#define SSP1DR         SSP1_BASE_ADDR + 0x08
+#define SSP1SR         SSP1_BASE_ADDR + 0x0C
+#define SSP1CPSR       SSP1_BASE_ADDR + 0x10
+#define SSP1IMSC       SSP1_BASE_ADDR + 0x14
+#define SSP1RIS        SSP1_BASE_ADDR + 0x18
+#define SSP1MIS        SSP1_BASE_ADDR + 0x1C
+#define SSP1ICR        SSP1_BASE_ADDR + 0x20
+#define SSP1DMACR      SSP1_BASE_ADDR + 0x24
+
+/* Real Time Clock */
+#define RTC_BASE_ADDR		0xE0024000
+#define RTC_ILR         RTC_BASE_ADDR + 0x00
+#define RTC_CTC         RTC_BASE_ADDR + 0x04
+#define RTC_CCR         RTC_BASE_ADDR + 0x08
+#define RTC_CIIR        RTC_BASE_ADDR + 0x0C
+#define RTC_AMR         RTC_BASE_ADDR + 0x10
+#define RTC_CTIME0      RTC_BASE_ADDR + 0x14
+#define RTC_CTIME1      RTC_BASE_ADDR + 0x18
+#define RTC_CTIME2      RTC_BASE_ADDR + 0x1C
+#define RTC_SEC         RTC_BASE_ADDR + 0x20
+#define RTC_MIN         RTC_BASE_ADDR + 0x24
+#define RTC_HOUR        RTC_BASE_ADDR + 0x28
+#define RTC_DOM         RTC_BASE_ADDR + 0x2C
+#define RTC_DOW         RTC_BASE_ADDR + 0x30
+#define RTC_DOY         RTC_BASE_ADDR + 0x34
+#define RTC_MONTH       RTC_BASE_ADDR + 0x38
+#define RTC_YEAR        RTC_BASE_ADDR + 0x3C
+#define RTC_CISS        RTC_BASE_ADDR + 0x40
+#define RTC_ALSEC       RTC_BASE_ADDR + 0x60
+#define RTC_ALMIN       RTC_BASE_ADDR + 0x64
+#define RTC_ALHOUR      RTC_BASE_ADDR + 0x68
+#define RTC_ALDOM       RTC_BASE_ADDR + 0x6C
+#define RTC_ALDOW       RTC_BASE_ADDR + 0x70
+#define RTC_ALDOY       RTC_BASE_ADDR + 0x74
+#define RTC_ALMON       RTC_BASE_ADDR + 0x78
+#define RTC_ALYEAR      RTC_BASE_ADDR + 0x7C
+#define RTC_PREINT      RTC_BASE_ADDR + 0x80
+#define RTC_PREFRAC     RTC_BASE_ADDR + 0x84
+
+/* A/D Converter 0 (AD0) */
+#define AD0_BASE_ADDR		0xE0034000
+#define AD0CR          AD0_BASE_ADDR + 0x00
+#define AD0GDR         AD0_BASE_ADDR + 0x04
+#define AD0INTEN       AD0_BASE_ADDR + 0x0C
+#define AD0DR0         AD0_BASE_ADDR + 0x10
+#define AD0DR1         AD0_BASE_ADDR + 0x14
+#define AD0DR2         AD0_BASE_ADDR + 0x18
+#define AD0DR3         AD0_BASE_ADDR + 0x1C
+#define AD0DR4         AD0_BASE_ADDR + 0x20
+#define AD0DR5         AD0_BASE_ADDR + 0x24
+#define AD0DR6         AD0_BASE_ADDR + 0x28
+#define AD0DR7         AD0_BASE_ADDR + 0x2C
+#define AD0STAT        AD0_BASE_ADDR + 0x30
+
+/* D/A Converter */
+#define DAC_BASE_ADDR		0xE006C000
+#define DACR           DAC_BASE_ADDR + 0x00
+
+/* Watchdog */
+#define WDG_BASE_ADDR		0xE0000000
+#define WDMOD          WDG_BASE_ADDR + 0x00
+#define WDTC           WDG_BASE_ADDR + 0x04
+#define WDFEED         WDG_BASE_ADDR + 0x08
+#define WDTV           WDG_BASE_ADDR + 0x0C
+#define WDCLKSEL       WDG_BASE_ADDR + 0x10
+
+/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
+#define CAN_ACCEPT_BASE_ADDR		0xE003C000
+#define CAN_AFMR	CAN_ACCEPT_BASE_ADDR + 0x00
+#define CAN_SFF_SA 	CAN_ACCEPT_BASE_ADDR + 0x04
+#define CAN_SFF_GRP_SA 	CAN_ACCEPT_BASE_ADDR + 0x08
+#define CAN_EFF_SA 	CAN_ACCEPT_BASE_ADDR + 0x0C
+#define CAN_EFF_GRP_SA 	CAN_ACCEPT_BASE_ADDR + 0x10
+#define CAN_EOT 	CAN_ACCEPT_BASE_ADDR + 0x14
+#define CAN_LUT_ERR_ADR CAN_ACCEPT_BASE_ADDR + 0x18
+#define CAN_LUT_ERR 	CAN_ACCEPT_BASE_ADDR + 0x1C
+
+#define CAN_CENTRAL_BASE_ADDR		0xE0040000
+#define CAN_TX_SR 	CAN_CENTRAL_BASE_ADDR + 0x00
+#define CAN_RX_SR 	CAN_CENTRAL_BASE_ADDR + 0x04
+#define CAN_MSR 	CAN_CENTRAL_BASE_ADDR + 0x08
+
+#define CAN1_BASE_ADDR		0xE0044000
+#define CAN1MOD 	CAN1_BASE_ADDR + 0x00
+#define CAN1CMR 	CAN1_BASE_ADDR + 0x04
+#define CAN1GSR 	CAN1_BASE_ADDR + 0x08
+#define CAN1ICR 	CAN1_BASE_ADDR + 0x0C
+#define CAN1IER 	CAN1_BASE_ADDR + 0x10
+#define CAN1BTR 	CAN1_BASE_ADDR + 0x14
+#define CAN1EWL 	CAN1_BASE_ADDR + 0x18
+#define CAN1SR 		CAN1_BASE_ADDR + 0x1C
+#define CAN1RFS 	CAN1_BASE_ADDR + 0x20
+#define CAN1RID 	CAN1_BASE_ADDR + 0x24
+#define CAN1RDA 	CAN1_BASE_ADDR + 0x28
+#define CAN1RDB 	CAN1_BASE_ADDR + 0x2C
+
+#define CAN1TFI1 	CAN1_BASE_ADDR + 0x30
+#define CAN1TID1 	CAN1_BASE_ADDR + 0x34
+#define CAN1TDA1 	CAN1_BASE_ADDR + 0x38
+#define CAN1TDB1 	CAN1_BASE_ADDR + 0x3C
+#define CAN1TFI2 	CAN1_BASE_ADDR + 0x40
+#define CAN1TID2 	CAN1_BASE_ADDR + 0x44
+#define CAN1TDA2 	CAN1_BASE_ADDR + 0x48
+#define CAN1TDB2 	CAN1_BASE_ADDR + 0x4C
+#define CAN1TFI3 	CAN1_BASE_ADDR + 0x50
+#define CAN1TID3 	CAN1_BASE_ADDR + 0x54
+#define CAN1TDA3 	CAN1_BASE_ADDR + 0x58
+#define CAN1TDB3 	CAN1_BASE_ADDR + 0x5C
+
+#define CAN2_BASE_ADDR		0xE0048000
+#define CAN2MOD 	CAN2_BASE_ADDR + 0x00
+#define CAN2CMR 	CAN2_BASE_ADDR + 0x04
+#define CAN2GSR 	CAN2_BASE_ADDR + 0x08
+#define CAN2ICR 	CAN2_BASE_ADDR + 0x0C
+#define CAN2IER 	CAN2_BASE_ADDR + 0x10
+#define CAN2BTR 	CAN2_BASE_ADDR + 0x14
+#define CAN2EWL 	CAN2_BASE_ADDR + 0x18
+#define CAN2SR 		CAN2_BASE_ADDR + 0x1C
+#define CAN2RFS 	CAN2_BASE_ADDR + 0x20
+#define CAN2RID 	CAN2_BASE_ADDR + 0x24
+#define CAN2RDA 	CAN2_BASE_ADDR + 0x28
+#define CAN2RDB 	CAN2_BASE_ADDR + 0x2C
+
+#define CAN2TFI1 	CAN2_BASE_ADDR + 0x30
+#define CAN2TID1 	CAN2_BASE_ADDR + 0x34
+#define CAN2TDA1 	CAN2_BASE_ADDR + 0x38
+#define CAN2TDB1 	CAN2_BASE_ADDR + 0x3C
+#define CAN2TFI2 	CAN2_BASE_ADDR + 0x40
+#define CAN2TID2 	CAN2_BASE_ADDR + 0x44
+#define CAN2TDA2 	CAN2_BASE_ADDR + 0x48
+#define CAN2TDB2 	CAN2_BASE_ADDR + 0x4C
+#define CAN2TFI3 	CAN2_BASE_ADDR + 0x50
+#define CAN2TID3 	CAN2_BASE_ADDR + 0x54
+#define CAN2TDA3 	CAN2_BASE_ADDR + 0x58
+#define CAN2TDB3 	CAN2_BASE_ADDR + 0x5C
+
+/* MultiMedia Card Interface(MCI) Controller */
+#define MCI_BASE_ADDR		0xE008C000
+#define MCI_POWER      MCI_BASE_ADDR + 0x00
+#define MCI_CLOCK      MCI_BASE_ADDR + 0x04
+#define MCI_ARGUMENT   MCI_BASE_ADDR + 0x08
+#define MCI_COMMAND    MCI_BASE_ADDR + 0x0C
+#define MCI_RESP_CMD   MCI_BASE_ADDR + 0x10
+#define MCI_RESP0      MCI_BASE_ADDR + 0x14
+#define MCI_RESP1      MCI_BASE_ADDR + 0x18
+#define MCI_RESP2      MCI_BASE_ADDR + 0x1C
+#define MCI_RESP3      MCI_BASE_ADDR + 0x20
+#define MCI_DATA_TMR   MCI_BASE_ADDR + 0x24
+#define MCI_DATA_LEN   MCI_BASE_ADDR + 0x28
+#define MCI_DATA_CTRL  MCI_BASE_ADDR + 0x2C
+#define MCI_DATA_CNT   MCI_BASE_ADDR + 0x30
+#define MCI_STATUS     MCI_BASE_ADDR + 0x34
+#define MCI_CLEAR      MCI_BASE_ADDR + 0x38
+#define MCI_MASK0      MCI_BASE_ADDR + 0x3C
+#define MCI_MASK1      MCI_BASE_ADDR + 0x40
+#define MCI_FIFO_CNT   MCI_BASE_ADDR + 0x48
+#define MCI_FIFO       MCI_BASE_ADDR + 0x80
+
+/* I2S Interface Controller (I2S) */
+#define I2S_BASE_ADDR		0xE0088000
+#define I2S_DAO        I2S_BASE_ADDR + 0x00
+#define I2S_DAI        I2S_BASE_ADDR + 0x04
+#define I2S_TX_FIFO    I2S_BASE_ADDR + 0x08
+#define I2S_RX_FIFO    I2S_BASE_ADDR + 0x0C
+#define I2S_STATE      I2S_BASE_ADDR + 0x10
+#define I2S_DMA1       I2S_BASE_ADDR + 0x14
+#define I2S_DMA2       I2S_BASE_ADDR + 0x18
+#define I2S_IRQ        I2S_BASE_ADDR + 0x1C
+#define I2S_TXRATE     I2S_BASE_ADDR + 0x20
+#define I2S_RXRATE     I2S_BASE_ADDR + 0x24
+
+/* General-purpose DMA Controller */
+#define DMA_BASE_ADDR		0xFFE04000
+#define GPDMA_INT_STAT         DMA_BASE_ADDR + 0x000
+#define GPDMA_INT_TCSTAT       DMA_BASE_ADDR + 0x004
+#define GPDMA_INT_TCCLR        DMA_BASE_ADDR + 0x008
+#define GPDMA_INT_ERR_STAT     DMA_BASE_ADDR + 0x00C
+#define GPDMA_INT_ERR_CLR      DMA_BASE_ADDR + 0x010
+#define GPDMA_RAW_INT_TCSTAT   DMA_BASE_ADDR + 0x014
+#define GPDMA_RAW_INT_ERR_STAT DMA_BASE_ADDR + 0x018
+#define GPDMA_ENABLED_CHNS     DMA_BASE_ADDR + 0x01C
+#define GPDMA_SOFT_BREQ        DMA_BASE_ADDR + 0x020
+#define GPDMA_SOFT_SREQ        DMA_BASE_ADDR + 0x024
+#define GPDMA_SOFT_LBREQ       DMA_BASE_ADDR + 0x028
+#define GPDMA_SOFT_LSREQ       DMA_BASE_ADDR + 0x02C
+#define GPDMA_CONFIG           DMA_BASE_ADDR + 0x030
+#define GPDMA_SYNC             DMA_BASE_ADDR + 0x034
+
+/* DMA channel 0 registers */
+#define GPDMA_CH0_SRC      DMA_BASE_ADDR + 0x100
+#define GPDMA_CH0_DEST     DMA_BASE_ADDR + 0x104
+#define GPDMA_CH0_LLI      DMA_BASE_ADDR + 0x108
+#define GPDMA_CH0_CTRL     DMA_BASE_ADDR + 0x10C
+#define GPDMA_CH0_CFG      DMA_BASE_ADDR + 0x110
+
+/* DMA channel 1 registers */
+#define GPDMA_CH1_SRC      DMA_BASE_ADDR + 0x120
+#define GPDMA_CH1_DEST     DMA_BASE_ADDR + 0x124
+#define GPDMA_CH1_LLI      DMA_BASE_ADDR + 0x128
+#define GPDMA_CH1_CTRL     DMA_BASE_ADDR + 0x12C
+#define GPDMA_CH1_CFG      DMA_BASE_ADDR + 0x130
+
+/* USB Controller */
+#define USB_INT_BASE_ADDR	0xE01FC1C0
+#define USB_BASE_ADDR		0xFFE0C200	/* USB Base Address */
+
+#define USB_INT_STAT    USB_INT_BASE_ADDR + 0x00
+
+/* USB Device Interrupt Registers */
+#define DEV_INT_STAT    USB_BASE_ADDR + 0x00
+#define DEV_INT_EN      USB_BASE_ADDR + 0x04
+#define DEV_INT_CLR     USB_BASE_ADDR + 0x08
+#define DEV_INT_SET     USB_BASE_ADDR + 0x0C
+#define DEV_INT_PRIO    USB_BASE_ADDR + 0x2C
+
+/* USB Device Endpoint Interrupt Registers */
+#define EP_INT_STAT     USB_BASE_ADDR + 0x30
+#define EP_INT_EN       USB_BASE_ADDR + 0x34
+#define EP_INT_CLR      USB_BASE_ADDR + 0x38
+#define EP_INT_SET      USB_BASE_ADDR + 0x3C
+#define EP_INT_PRIO     USB_BASE_ADDR + 0x40
+
+/* USB Device Endpoint Realization Registers */
+#define REALIZE_EP      USB_BASE_ADDR + 0x44
+#define EP_INDEX        USB_BASE_ADDR + 0x48
+#define MAXPACKET_SIZE  USB_BASE_ADDR + 0x4C
+
+/* USB Device Command Reagisters */
+#define CMD_CODE        USB_BASE_ADDR + 0x10
+#define CMD_DATA        USB_BASE_ADDR + 0x14
+
+/* USB Device Data Transfer Registers */
+#define RX_DATA         USB_BASE_ADDR + 0x18
+#define TX_DATA         USB_BASE_ADDR + 0x1C
+#define RX_PLENGTH      USB_BASE_ADDR + 0x20
+#define TX_PLENGTH      USB_BASE_ADDR + 0x24
+#define USB_CTRL        USB_BASE_ADDR + 0x28
+
+/* USB Device DMA Registers */
+#define DMA_REQ_STAT        USB_BASE_ADDR + 0x50
+#define DMA_REQ_CLR         USB_BASE_ADDR + 0x54
+#define DMA_REQ_SET         USB_BASE_ADDR + 0x58
+#define UDCA_HEAD           USB_BASE_ADDR + 0x80
+#define EP_DMA_STAT         USB_BASE_ADDR + 0x84
+#define EP_DMA_EN           USB_BASE_ADDR + 0x88
+#define EP_DMA_DIS          USB_BASE_ADDR + 0x8C
+#define DMA_INT_STAT        USB_BASE_ADDR + 0x90
+#define DMA_INT_EN          USB_BASE_ADDR + 0x94
+#define EOT_INT_STAT        USB_BASE_ADDR + 0xA0
+#define EOT_INT_CLR         USB_BASE_ADDR + 0xA4
+#define EOT_INT_SET         USB_BASE_ADDR + 0xA8
+#define NDD_REQ_INT_STAT    USB_BASE_ADDR + 0xAC
+#define NDD_REQ_INT_CLR     USB_BASE_ADDR + 0xB0
+#define NDD_REQ_INT_SET     USB_BASE_ADDR + 0xB4
+#define SYS_ERR_INT_STAT    USB_BASE_ADDR + 0xB8
+#define SYS_ERR_INT_CLR     USB_BASE_ADDR + 0xBC
+#define SYS_ERR_INT_SET     USB_BASE_ADDR + 0xC0
+
+/* USB Host Controller */
+#define USBHC_BASE_ADDR		0xFFE0C000
+#define HC_REVISION         USBHC_BASE_ADDR + 0x00
+#define HC_CONTROL          USBHC_BASE_ADDR + 0x04
+#define HC_CMD_STAT         USBHC_BASE_ADDR + 0x08
+#define HC_INT_STAT         USBHC_BASE_ADDR + 0x0C
+#define HC_INT_EN           USBHC_BASE_ADDR + 0x10
+#define HC_INT_DIS          USBHC_BASE_ADDR + 0x14
+#define HC_HCCA             USBHC_BASE_ADDR + 0x18
+#define HC_PERIOD_CUR_ED    USBHC_BASE_ADDR + 0x1C
+#define HC_CTRL_HEAD_ED     USBHC_BASE_ADDR + 0x20
+#define HC_CTRL_CUR_ED      USBHC_BASE_ADDR + 0x24
+#define HC_BULK_HEAD_ED     USBHC_BASE_ADDR + 0x28
+#define HC_BULK_CUR_ED      USBHC_BASE_ADDR + 0x2C
+#define HC_DONE_HEAD        USBHC_BASE_ADDR + 0x30
+#define HC_FM_INTERVAL      USBHC_BASE_ADDR + 0x34
+#define HC_FM_REMAINING     USBHC_BASE_ADDR + 0x38
+#define HC_FM_NUMBER        USBHC_BASE_ADDR + 0x3C
+#define HC_PERIOD_START     USBHC_BASE_ADDR + 0x40
+#define HC_LS_THRHLD        USBHC_BASE_ADDR + 0x44
+#define HC_RH_DESCA         USBHC_BASE_ADDR + 0x48
+#define HC_RH_DESCB         USBHC_BASE_ADDR + 0x4C
+#define HC_RH_STAT          USBHC_BASE_ADDR + 0x50
+#define HC_RH_PORT_STAT1    USBHC_BASE_ADDR + 0x54
+#define HC_RH_PORT_STAT2    USBHC_BASE_ADDR + 0x58
+
+/* USB OTG Controller */
+#define USBOTG_BASE_ADDR	0xFFE0C100
+#define OTG_INT_STAT        USBOTG_BASE_ADDR + 0x00
+#define OTG_INT_EN          USBOTG_BASE_ADDR + 0x04
+#define OTG_INT_SET         USBOTG_BASE_ADDR + 0x08
+#define OTG_INT_CLR         USBOTG_BASE_ADDR + 0x0C
+#define OTG_STAT_CTRL       USBOTG_BASE_ADDR + 0x10
+#define OTG_TIMER           USBOTG_BASE_ADDR + 0x14
+
+#define USBOTG_I2C_BASE_ADDR	0xFFE0C300
+#define OTG_I2C_RX          USBOTG_I2C_BASE_ADDR + 0x00
+#define OTG_I2C_TX          USBOTG_I2C_BASE_ADDR + 0x00
+#define OTG_I2C_STS         USBOTG_I2C_BASE_ADDR + 0x04
+#define OTG_I2C_CTL         USBOTG_I2C_BASE_ADDR + 0x08
+#define OTG_I2C_CLKHI       USBOTG_I2C_BASE_ADDR + 0x0C
+#define OTG_I2C_CLKLO       USBOTG_I2C_BASE_ADDR + 0x10
+
+#define USBOTG_CLK_BASE_ADDR	0xFFE0CFF0
+#define OTG_CLK_CTRL        USBOTG_CLK_BASE_ADDR + 0x04
+#define OTG_CLK_STAT        USBOTG_CLK_BASE_ADDR + 0x08
+
+/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
+#define MAC_BASE_ADDR		0xFFE00000	/* AHB Peripheral # 0 */
+#define MAC_MAC1            MAC_BASE_ADDR + 0x000	/* MAC config reg 1 */
+#define MAC_MAC2            MAC_BASE_ADDR + 0x004	/* MAC config reg 2 */
+#define MAC_IPGT            MAC_BASE_ADDR + 0x008	/* b2b InterPacketGap reg */
+#define MAC_IPGR            MAC_BASE_ADDR + 0x00C	/* non b2b InterPacketGap reg */
+#define MAC_CLRT            MAC_BASE_ADDR + 0x010	/* CoLlision window/ReTry reg */
+#define MAC_MAXF            MAC_BASE_ADDR + 0x014	/* MAXimum Frame reg */
+#define MAC_SUPP            MAC_BASE_ADDR + 0x018	/* PHY SUPPort reg */
+#define MAC_TEST            MAC_BASE_ADDR + 0x01C	/* TEST reg */
+#define MAC_MCFG            MAC_BASE_ADDR + 0x020	/* MII Mgmt ConFiG reg */
+#define MAC_MCMD            MAC_BASE_ADDR + 0x024	/* MII Mgmt CoMmanD reg */
+#define MAC_MADR            MAC_BASE_ADDR + 0x028	/* MII Mgmt ADdRess reg */
+#define MAC_MWTD            MAC_BASE_ADDR + 0x02C	/* MII Mgmt WriTe Data reg (WO) */
+#define MAC_MRDD            MAC_BASE_ADDR + 0x030	/* MII Mgmt ReaD Data reg (RO) */
+#define MAC_MIND            MAC_BASE_ADDR + 0x034	/* MII Mgmt INDicators reg (RO) */
+
+#define MAC_SA0             MAC_BASE_ADDR + 0x040	/* Station Address 0 reg */
+#define MAC_SA1             MAC_BASE_ADDR + 0x044	/* Station Address 1 reg */
+#define MAC_SA2             MAC_BASE_ADDR + 0x048	/* Station Address 2 reg */
+
+#define MAC_COMMAND         MAC_BASE_ADDR + 0x100	/* Command reg */
+#define MAC_STATUS          MAC_BASE_ADDR + 0x104	/* Status reg (RO) */
+#define MAC_RXDESCRIPTOR    MAC_BASE_ADDR + 0x108	/* Rx descriptor base address reg */
+#define MAC_RXSTATUS        MAC_BASE_ADDR + 0x10C	/* Rx status base address reg */
+#define MAC_RXDESCRIPTORNUM MAC_BASE_ADDR + 0x110	/* Rx number of descriptors reg */
+#define MAC_RXPRODUCEINDEX  MAC_BASE_ADDR + 0x114	/* Rx produce index reg (RO) */
+#define MAC_RXCONSUMEINDEX  MAC_BASE_ADDR + 0x118	/* Rx consume index reg */
+#define MAC_TXDESCRIPTOR    MAC_BASE_ADDR + 0x11C	/* Tx descriptor base address reg */
+#define MAC_TXSTATUS        MAC_BASE_ADDR + 0x120	/* Tx status base address reg */
+#define MAC_TXDESCRIPTORNUM MAC_BASE_ADDR + 0x124	/* Tx number of descriptors reg */
+#define MAC_TXPRODUCEINDEX  MAC_BASE_ADDR + 0x128	/* Tx produce index reg */
+#define MAC_TXCONSUMEINDEX  MAC_BASE_ADDR + 0x12C	/* Tx consume index reg (RO) */
+
+#define MAC_TSV0            MAC_BASE_ADDR + 0x158	/* Tx status vector 0 reg (RO) */
+#define MAC_TSV1            MAC_BASE_ADDR + 0x15C	/* Tx status vector 1 reg (RO) */
+#define MAC_RSV             MAC_BASE_ADDR + 0x160	/* Rx status vector reg (RO) */
+
+#define MAC_FLOWCONTROLCNT  MAC_BASE_ADDR + 0x170	/* Flow control counter reg */
+#define MAC_FLOWCONTROLSTS  MAC_BASE_ADDR + 0x174	/* Flow control status reg */
+
+#define MAC_RXFILTERCTRL    MAC_BASE_ADDR + 0x200	/* Rx filter ctrl reg */
+#define MAC_RXFILTERWOLSTS  MAC_BASE_ADDR + 0x204	/* Rx filter WoL status reg (RO) */
+#define MAC_RXFILTERWOLCLR  MAC_BASE_ADDR + 0x208	/* Rx filter WoL clear reg (WO) */
+
+#define MAC_HASHFILTERL     MAC_BASE_ADDR + 0x210	/* Hash filter LSBs reg */
+#define MAC_HASHFILTERH     MAC_BASE_ADDR + 0x214	/* Hash filter MSBs reg */
+
+#define MAC_INTSTATUS       MAC_BASE_ADDR + 0xFE0	/* Interrupt status reg (RO) */
+#define MAC_INTENABLE       MAC_BASE_ADDR + 0xFE4	/* Interrupt enable reg  */
+#define MAC_INTCLEAR        MAC_BASE_ADDR + 0xFE8	/* Interrupt clear reg (WO) */
+#define MAC_INTSET          MAC_BASE_ADDR + 0xFEC	/* Interrupt set reg (WO) */
+
+#define MAC_POWERDOWN       MAC_BASE_ADDR + 0xFF4	/* Power-down reg */
+#define MAC_MODULEID        MAC_BASE_ADDR + 0xFFC	/* Module ID reg (RO) */
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#endif
diff -upNr u-boot-orig/include/flash.h u-boot/include/flash.h
--- u-boot-orig/include/flash.h	2009-03-18 00:42:12.000000000 +0100
+++ u-boot/include/flash.h	2009-03-19 11:24:32.000000000 +0100
@@ -327,154 +329,153 @@ extern flash_info_t *flash_get_info(ulon
  #define INTEL_ID_28F256P30T 0x88198819	/* 256M = 128K x 255 + 32k x 4 */
  #define INTEL_ID_28F256P30B 0x881C881C	/* 256M = 128K x 255 + 32k x 4 */
-#define INTEL_ID_28F160S3   0x00D000D0	/*  16M = 512K x  32 (64kB x 32)	*/
-#define INTEL_ID_28F320S3   0x00D400D4	/*  32M = 512K x  64 (64kB x 64)	*/
+#define INTEL_ID_28F160S3   0x00D000D0	/*  16M = 512K x  32 (64kB x 32)        */
+#define INTEL_ID_28F320S3   0x00D400D4	/*  32M = 512K x  64 (64kB x 64)        */
/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */
-#define SHARP_ID_28F016SCL  0xAAAAAAAA	/* LH28F016SCT-L95 2Mx8, 32 64k blocks	*/
-#define SHARP_ID_28F016SCZ  0xA0A0A0A0	/* LH28F016SCT-Z4  2Mx8, 32 64k blocks	*/
-#define SHARP_ID_28F008SC   0xA6A6A6A6	/* LH28F008SCT-L12 1Mx8, 16 64k blocks	*/
-					/* LH28F008SCR-L85 1Mx8, 16 64k blocks	*/
-
-#define TOSH_ID_FVT160	0xC2		/* TC58FVT160 ID (16 M, top )		*/
-#define TOSH_ID_FVB160	0x43		/* TC58FVT160 ID (16 M, bottom )	*/
-#define PHILIPS_LPC2292 0x0401FF13  /* LPC2292 internal FLASH			*/
-
+#define SHARP_ID_28F016SCL  0xAAAAAAAA	/* LH28F016SCT-L95 2Mx8, 32 64k blocks  */
+#define SHARP_ID_28F016SCZ  0xA0A0A0A0	/* LH28F016SCT-Z4  2Mx8, 32 64k blocks  */
+#define SHARP_ID_28F008SC   0xA6A6A6A6	/* LH28F008SCT-L12 1Mx8, 16 64k blocks  */
+					/* LH28F008SCR-L85 1Mx8, 16 64k blocks  */
+
+#define TOSH_ID_FVT160	0xC2	/* TC58FVT160 ID (16 M, top )           */
+#define TOSH_ID_FVB160	0x43	/* TC58FVT160 ID (16 M, bottom )        */
+#define PHILIPS_LPC2292 0x0401FF13	/* LPC2292 internal FLASH               */
+#define PHILIPS_LPC2468 0x0603FF35	/* LPC2468 internal FLASH               */
  /*-----------------------------------------------------------------------
   * Internal FLASH identification codes
   *
   * Be careful when adding new type! Odd numbers are "bottom boot sector" types!
   */
-#define FLASH_AM040	0x0001		/* AMD Am29F040B, Am29LV040B		*/
-					/* Bright Micro BM29F040		*/
-					/* Fujitsu MBM29F040A			*/
-					/* STM M29W040B				*/
-					/* SGS Thomson M29F040B			*/
-					/* 8 64K x 8 uniform sectors		*/
-#define FLASH_AM400T	0x0002		/* AMD AM29LV400			*/
+#define FLASH_AM040	0x0001	/* AMD Am29F040B, Am29LV040B            */
+					/* Bright Micro BM29F040                */
+					/* Fujitsu MBM29F040A                   */
+					/* STM M29W040B                         */
+					/* SGS Thomson M29F040B                 */
+					/* 8 64K x 8 uniform sectors            */
+#define FLASH_AM400T	0x0002	/* AMD AM29LV400                        */
  #define FLASH_AM400B	0x0003
-#define FLASH_AM800T	0x0004		/* AMD AM29LV800			*/
+#define FLASH_AM800T	0x0004	/* AMD AM29LV800                        */
  #define FLASH_AM800B	0x0005
-#define FLASH_AM116DT	0x0026		/* AMD AM29LV116DT (2Mx8bit) */
-#define FLASH_AM116DB	0x0027		/* AMD AM29LV116DB (2Mx8bit) */
-#define FLASH_AM160T	0x0006		/* AMD AM29LV160			*/
-#define FLASH_AM160LV	0x0046		/* AMD29LV160DB (2M = 2Mx8bit ) */
+#define FLASH_AM116DT	0x0026	/* AMD AM29LV116DT (2Mx8bit) */
+#define FLASH_AM116DB	0x0027	/* AMD AM29LV116DB (2Mx8bit) */
+#define FLASH_AM160T	0x0006	/* AMD AM29LV160                        */
+#define FLASH_AM160LV	0x0046	/* AMD29LV160DB (2M = 2Mx8bit ) */
  #define FLASH_AM160B	0x0007
-#define FLASH_AM320T	0x0008		/* AMD AM29LV320			*/
+#define FLASH_AM320T	0x0008	/* AMD AM29LV320                        */
  #define FLASH_AM320B	0x0009
-#define FLASH_AM080	0x000A		/* AMD Am29F080B			*/
-					/* 16 64K x 8 uniform sectors		*/
+#define FLASH_AM080	0x000A	/* AMD Am29F080B                        */
+					/* 16 64K x 8 uniform sectors           */
-#define FLASH_AMDL322T	0x0010		/* AMD AM29DL322			*/
+#define FLASH_AMDL322T	0x0010	/* AMD AM29DL322                        */
  #define FLASH_AMDL322B	0x0011
-#define FLASH_AMDL323T	0x0012		/* AMD AM29DL323			*/
+#define FLASH_AMDL323T	0x0012	/* AMD AM29DL323                        */
  #define FLASH_AMDL323B	0x0013
-#define FLASH_AMDL324T	0x0014		/* AMD AM29DL324			*/
+#define FLASH_AMDL324T	0x0014	/* AMD AM29DL324                        */
  #define FLASH_AMDL324B	0x0015
#define FLASH_AMDLV033C 0x0018
  #define FLASH_AMDLV065D 0x001A
-#define FLASH_AMDL640	0x0016		/* AMD AM29DL640D			*/
-#define FLASH_AMD016	0x0018		/* AMD AM29F016D			*/
-#define FLASH_AMDL640MB 0x0019		/* AMD AM29LV640MB (64M, bottom boot sect)*/
-#define FLASH_AMDL640MT 0x001A		/* AMD AM29LV640MT (64M, top boot sect) */
-
-#define FLASH_SST200A	0x0040		/* SST 39xF200A ID (  2M = 128K x 16 )	*/
-#define FLASH_SST400A	0x0042		/* SST 39xF400A ID (  4M = 256K x 16 )	*/
-#define FLASH_SST800A	0x0044		/* SST 39xF800A ID (  8M = 512K x 16 )	*/
-#define FLASH_SST160A	0x0046		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
-#define FLASH_SST320	0x0048		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
-#define FLASH_SST640	0x004A		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
-#define FLASH_SST020	0x0024		/* SST 39xF020 ID (256KB = 2Mbit x 8 )	*/
-#define FLASH_SST040	0x000E		/* SST 39xF040 ID (512KB = 4Mbit x 8 )	*/
-
-#define FLASH_STM800AB	0x0051		/* STM M29WF800AB  (  8M = 512K x 16 )	*/
-#define FLASH_STMW320DT 0x0052		/* STM M29W320DT   (32 M, top boot sector)	*/
-#define FLASH_STMW320DB 0x0053		/* STM M29W320DB   (32 M, bottom boot sect)*/
-#define FLASH_STM320DB	0x00CB		/* STM M29W320DB (4M = 64K x 64, bottom)*/
-#define FLASH_STM800DT	0x00D7		/* STM M29W800DT (1M = 64K x 16, top)	*/
-#define FLASH_STM800DB	0x005B		/* STM M29W800DB (1M = 64K x 16, bottom)*/
-
-#define FLASH_28F400_T	0x0062		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
-#define FLASH_28F400_B	0x0063		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
-
-#define FLASH_INTEL800T 0x0074		/* INTEL 28F800B3T (  8M = 512K x 16 )	*/
-#define FLASH_INTEL800B 0x0075		/* INTEL 28F800B3B (  8M = 512K x 16 )	*/
-#define FLASH_INTEL160T 0x0076		/* INTEL 28F160B3T ( 16M =  1 M x 16 )	*/
-#define FLASH_INTEL160B 0x0077		/* INTEL 28F160B3B ( 16M =  1 M x 16 )	*/
-#define FLASH_INTEL320T 0x0078		/* INTEL 28F320B3T ( 32M =  2 M x 16 )	*/
-#define FLASH_INTEL320B 0x0079		/* INTEL 28F320B3B ( 32M =  2 M x 16 )	*/
-#define FLASH_INTEL640T 0x007A		/* INTEL 28F320B3T ( 64M =  4 M x 16 )	*/
-#define FLASH_INTEL640B 0x007B		/* INTEL 28F320B3B ( 64M =  4 M x 16 )	*/
-
-#define FLASH_28F008S5	0x0080		/* Intel 28F008S5  (  1M =  64K x 16 )	*/
-#define FLASH_28F016SV	0x0081		/* Intel 28F016SV  ( 16M = 512k x 32 )	*/
-#define FLASH_28F800_B	0x0083		/* Intel E28F800B  (  1M = ? )		*/
-#define FLASH_AM29F800B 0x0084		/* AMD Am29F800BB  (  1M = ? )		*/
-#define FLASH_28F320J5	0x0085		/* Intel 28F320J5  (  4M = 128K x 32 )	*/
-#define FLASH_28F160S3	0x0086		/* Intel 28F160S3  ( 16M = 512K x 32 )	*/
-#define FLASH_28F320S3	0x0088		/* Intel 28F320S3  ( 32M = 512K x 64 )	*/
-#define FLASH_AM640U	0x0090		/* AMD Am29LV640U  ( 64M = 4M x 16 )	*/
-#define FLASH_AM033C	0x0091		/* AMD AM29LV033   ( 32M = 4M x 8 )	*/
+#define FLASH_AMDL640	0x0016	/* AMD AM29DL640D                       */
+#define FLASH_AMD016	0x0018	/* AMD AM29F016D                        */
+#define FLASH_AMDL640MB 0x0019	/* AMD AM29LV640MB (64M, bottom boot sect) */
+#define FLASH_AMDL640MT 0x001A	/* AMD AM29LV640MT (64M, top boot sect) */
+
+#define FLASH_SST200A	0x0040	/* SST 39xF200A ID (  2M = 128K x 16 )  */
+#define FLASH_SST400A	0x0042	/* SST 39xF400A ID (  4M = 256K x 16 )  */
+#define FLASH_SST800A	0x0044	/* SST 39xF800A ID (  8M = 512K x 16 )  */
+#define FLASH_SST160A	0x0046	/* SST 39xF160A ID ( 16M =   1M x 16 )  */
+#define FLASH_SST320	0x0048	/* SST 39xF160A ID ( 16M =   1M x 16 )  */
+#define FLASH_SST640	0x004A	/* SST 39xF160A ID ( 16M =   1M x 16 )  */
+#define FLASH_SST020	0x0024	/* SST 39xF020 ID (256KB = 2Mbit x 8 )  */
+#define FLASH_SST040	0x000E	/* SST 39xF040 ID (512KB = 4Mbit x 8 )  */
+
+#define FLASH_STM800AB	0x0051	/* STM M29WF800AB  (  8M = 512K x 16 )  */
+#define FLASH_STMW320DT 0x0052	/* STM M29W320DT   (32 M, top boot sector)      */
+#define FLASH_STMW320DB 0x0053	/* STM M29W320DB   (32 M, bottom boot sect) */
+#define FLASH_STM320DB	0x00CB	/* STM M29W320DB (4M = 64K x 64, bottom) */
+#define FLASH_STM800DT	0x00D7	/* STM M29W800DT (1M = 64K x 16, top)   */
+#define FLASH_STM800DB	0x005B	/* STM M29W800DB (1M = 64K x 16, bottom) */
+
+#define FLASH_28F400_T	0x0062	/* MT  28F400B3 ID (  4M = 256K x 16 )  */
+#define FLASH_28F400_B	0x0063	/* MT  28F400B3 ID (  4M = 256K x 16 )  */
+
+#define FLASH_INTEL800T 0x0074	/* INTEL 28F800B3T (  8M = 512K x 16 )  */
+#define FLASH_INTEL800B 0x0075	/* INTEL 28F800B3B (  8M = 512K x 16 )  */
+#define FLASH_INTEL160T 0x0076	/* INTEL 28F160B3T ( 16M =  1 M x 16 )  */
+#define FLASH_INTEL160B 0x0077	/* INTEL 28F160B3B ( 16M =  1 M x 16 )  */
+#define FLASH_INTEL320T 0x0078	/* INTEL 28F320B3T ( 32M =  2 M x 16 )  */
+#define FLASH_INTEL320B 0x0079	/* INTEL 28F320B3B ( 32M =  2 M x 16 )  */
+#define FLASH_INTEL640T 0x007A	/* INTEL 28F320B3T ( 64M =  4 M x 16 )  */
+#define FLASH_INTEL640B 0x007B	/* INTEL 28F320B3B ( 64M =  4 M x 16 )  */
+
+#define FLASH_28F008S5	0x0080	/* Intel 28F008S5  (  1M =  64K x 16 )  */
+#define FLASH_28F016SV	0x0081	/* Intel 28F016SV  ( 16M = 512k x 32 )  */
+#define FLASH_28F800_B	0x0083	/* Intel E28F800B  (  1M = ? )          */
+#define FLASH_AM29F800B 0x0084	/* AMD Am29F800BB  (  1M = ? )          */
+#define FLASH_28F320J5	0x0085	/* Intel 28F320J5  (  4M = 128K x 32 )  */
+#define FLASH_28F160S3	0x0086	/* Intel 28F160S3  ( 16M = 512K x 32 )  */
+#define FLASH_28F320S3	0x0088	/* Intel 28F320S3  ( 32M = 512K x 64 )  */
+#define FLASH_AM640U	0x0090	/* AMD Am29LV640U  ( 64M = 4M x 16 )    */
+#define FLASH_AM033C	0x0091	/* AMD AM29LV033   ( 32M = 4M x 8 )     */
  #define FLASH_LH28F016SCT 0x0092	/* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
-#define FLASH_28F160F3B 0x0093		/* Intel 28F160F3B ( 16M = 1M x 16 )	*/
+#define FLASH_28F160F3B 0x0093	/* Intel 28F160F3B ( 16M = 1M x 16 )    */
  #define FLASH_AM065D	0x0093
-#define FLASH_28F640J5	0x0099		/* INTEL 28F640J5  ( 64M = 128K x  64)	*/
+#define FLASH_28F640J5	0x0099	/* INTEL 28F640J5  ( 64M = 128K x  64)  */
-#define FLASH_28F800C3T 0x009A		/* Intel 28F800C3T (  8M = 512K x 16 )	*/
-#define FLASH_28F800C3B 0x009B		/* Intel 28F800C3B (  8M = 512K x 16 )	*/
-#define FLASH_28F160C3T 0x009C		/* Intel 28F160C3T ( 16M = 1M x 16 )	*/
-#define FLASH_28F160C3B 0x009D		/* Intel 28F160C3B ( 16M = 1M x 16 )	*/
-#define FLASH_28F320C3T 0x009E		/* Intel 28F320C3T ( 32M = 2M x 16 )	*/
-#define FLASH_28F320C3B 0x009F		/* Intel 28F320C3B ( 32M = 2M x 16 )	*/
-#define FLASH_28F640C3T 0x00A0		/* Intel 28F640C3T ( 64M = 4M x 16 )	*/
-#define FLASH_28F640C3B 0x00A1		/* Intel 28F640C3B ( 64M = 4M x 16 )	*/
-#define FLASH_AMLV320U	0x00A2		/* AMD 29LV320M	   ( 32M = 2M x 16 )	*/
-
-#define FLASH_AM033	0x00A3		/* AMD AmL033C90V1   (32M = 4M x 8)	*/
-#define FLASH_AM065	0x0093		/* AMD AmL065DU12RI  (64M = 8M x 8)	*/
-#define FLASH_AT040	0x00A5		/* Amtel AT49LV040   (4M = 512K x 8)	*/
-
-#define FLASH_AMLV640U	0x00A4		/* AMD 29LV640M	   ( 64M = 4M x 16 )	*/
-#define FLASH_AMLV128U	0x00A6		/* AMD 29LV128M	   ( 128M = 8M x 16 )	*/
-#define FLASH_AMLV320B	0x00A7		/* AMD 29LV320MB   ( 32M = 2M x 16 )	*/
-#define FLASH_AMLV320T	0x00A8		/* AMD 29LV320MT   ( 32M = 2M x 16 )	*/
-#define FLASH_AMLV256U	0x00AA		/* AMD 29LV256M	   ( 256M = 16M x 16 )	*/
-#define FLASH_MXLV320B	0x00AB		/* MX  29LV320MB   ( 32M = 2M x 16 )	*/
-#define FLASH_MXLV320T	0x00AC		/* MX  29LV320MT   ( 32M = 2M x 16 )	*/
-#define FLASH_28F256L18T 0x00B0		/* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
-#define FLASH_AMDL163T	0x00B2		/* AMD AM29DL163T (2M x 16 )			*/
+#define FLASH_28F800C3T 0x009A	/* Intel 28F800C3T (  8M = 512K x 16 )  */
+#define FLASH_28F800C3B 0x009B	/* Intel 28F800C3B (  8M = 512K x 16 )  */
+#define FLASH_28F160C3T 0x009C	/* Intel 28F160C3T ( 16M = 1M x 16 )    */
+#define FLASH_28F160C3B 0x009D	/* Intel 28F160C3B ( 16M = 1M x 16 )    */
+#define FLASH_28F320C3T 0x009E	/* Intel 28F320C3T ( 32M = 2M x 16 )    */
+#define FLASH_28F320C3B 0x009F	/* Intel 28F320C3B ( 32M = 2M x 16 )    */
+#define FLASH_28F640C3T 0x00A0	/* Intel 28F640C3T ( 64M = 4M x 16 )    */
+#define FLASH_28F640C3B 0x00A1	/* Intel 28F640C3B ( 64M = 4M x 16 )    */
+#define FLASH_AMLV320U	0x00A2	/* AMD 29LV320M    ( 32M = 2M x 16 )    */
+
+#define FLASH_AM033	0x00A3	/* AMD AmL033C90V1   (32M = 4M x 8)     */
+#define FLASH_AM065	0x0093	/* AMD AmL065DU12RI  (64M = 8M x 8)     */
+#define FLASH_AT040	0x00A5	/* Amtel AT49LV040   (4M = 512K x 8)    */
+
+#define FLASH_AMLV640U	0x00A4	/* AMD 29LV640M    ( 64M = 4M x 16 )    */
+#define FLASH_AMLV128U	0x00A6	/* AMD 29LV128M    ( 128M = 8M x 16 )   */
+#define FLASH_AMLV320B	0x00A7	/* AMD 29LV320MB   ( 32M = 2M x 16 )    */
+#define FLASH_AMLV320T	0x00A8	/* AMD 29LV320MT   ( 32M = 2M x 16 )    */
+#define FLASH_AMLV256U	0x00AA	/* AMD 29LV256M    ( 256M = 16M x 16 )  */
+#define FLASH_MXLV320B	0x00AB	/* MX  29LV320MB   ( 32M = 2M x 16 )    */
+#define FLASH_MXLV320T	0x00AC	/* MX  29LV320MT   ( 32M = 2M x 16 )    */
+#define FLASH_28F256L18T 0x00B0	/* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
+#define FLASH_AMDL163T	0x00B2	/* AMD AM29DL163T (2M x 16 )                    */
  #define FLASH_AMDL163B	0x00B3
-#define FLASH_28F64K3	0x00B4		/* Intel 28F64K3   (  64M)		*/
-#define FLASH_28F128K3	0x00B6		/* Intel 28F128K3  ( 128M = 8M x 16 )	*/
-#define FLASH_28F256K3	0x00B8		/* Intel 28F256K3  ( 256M = 16M x 16 )	*/
-
-#define FLASH_28F320J3A 0x00C0		/* INTEL 28F320J3A ( 32M = 128K x  32)	*/
-#define FLASH_28F640J3A 0x00C2		/* INTEL 28F640J3A ( 64M = 128K x  64)	*/
-#define FLASH_28F128J3A 0x00C4		/* INTEL 28F128J3A (128M = 128K x 128)	*/
-#define FLASH_28F256J3A 0x00C6		/* INTEL 28F256J3A (256M = 128K x 256)	*/
-
-#define FLASH_FUJLV650	0x00D0		/* Fujitsu MBM 29LV650UE/651UE		*/
-#define FLASH_MT28S4M16LC 0x00E1	/* Micron MT28S4M16LC			*/
-#define FLASH_S29GL064M 0x00F0		/* Spansion S29GL064M-R6		*/
-#define FLASH_S29GL128N 0x00F1		/* Spansion S29GL128N			*/
-
-#define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
+#define FLASH_28F64K3	0x00B4	/* Intel 28F64K3   (  64M)              */
+#define FLASH_28F128K3	0x00B6	/* Intel 28F128K3  ( 128M = 8M x 16 )   */
+#define FLASH_28F256K3	0x00B8	/* Intel 28F256K3  ( 256M = 16M x 16 )  */
+
+#define FLASH_28F320J3A 0x00C0	/* INTEL 28F320J3A ( 32M = 128K x  32)  */
+#define FLASH_28F640J3A 0x00C2	/* INTEL 28F640J3A ( 64M = 128K x  64)  */
+#define FLASH_28F128J3A 0x00C4	/* INTEL 28F128J3A (128M = 128K x 128)  */
+#define FLASH_28F256J3A 0x00C6	/* INTEL 28F256J3A (256M = 128K x 256)  */
+
+#define FLASH_FUJLV650	0x00D0	/* Fujitsu MBM 29LV650UE/651UE          */
+#define FLASH_MT28S4M16LC 0x00E1	/* Micron MT28S4M16LC                   */
+#define FLASH_S29GL064M 0x00F0	/* Spansion S29GL064M-R6                */
+#define FLASH_S29GL128N 0x00F1	/* Spansion S29GL128N                   */
+#define FLASH_UNKNOWN	0xFFFF	/* unknown flash type                   */
/* manufacturer offsets
   */
-#define FLASH_MAN_AMD	0x00000000	/* AMD					*/
-#define FLASH_MAN_FUJ	0x00010000	/* Fujitsu				*/
-#define FLASH_MAN_BM	0x00020000	/* Bright Microelectronics		*/
-#define FLASH_MAN_MX	0x00030000	/* MXIC					*/
+#define FLASH_MAN_AMD	0x00000000	/* AMD                                  */
+#define FLASH_MAN_FUJ	0x00010000	/* Fujitsu                              */
+#define FLASH_MAN_BM	0x00020000	/* Bright Microelectronics              */
+#define FLASH_MAN_MX	0x00030000	/* MXIC                                 */
  #define FLASH_MAN_STM	0x00040000
-#define FLASH_MAN_TOSH	0x00050000	/* Toshiba				*/
-#define FLASH_MAN_EXCEL 0x00060000	/* Excel Semiconductor			*/
+#define FLASH_MAN_TOSH	0x00050000	/* Toshiba                              */
+#define FLASH_MAN_EXCEL 0x00060000	/* Excel Semiconductor                  */
  #define FLASH_MAN_SST	0x00100000
  #define FLASH_MAN_INTEL 0x00300000
  #define FLASH_MAN_MT	0x00400000
@@ -482,15 +483,14 @@ extern flash_info_t *flash_get_info(ulon
  #define FLASH_MAN_ATM	0x00600000
  #define FLASH_MAN_CFI	0x01000000
+#define FLASH_TYPEMASK	0x0000FFFF	/* extract FLASH type   information     */
+#define FLASH_VENDMASK	0xFFFF0000	/* extract FLASH vendor information     */
-#define FLASH_TYPEMASK	0x0000FFFF	/* extract FLASH type	information	*/
-#define FLASH_VENDMASK	0xFFFF0000	/* extract FLASH vendor information	*/
-
-#define FLASH_AMD_COMP	0x000FFFFF	/* Up to this ID, FLASH is compatible	*/
-					/* with AMD, Fujitsu and SST		*/
-					/* (JEDEC standard commands ?)		*/
+#define FLASH_AMD_COMP	0x000FFFFF	/* Up to this ID, FLASH is compatible   */
+					/* with AMD, Fujitsu and SST            */
+					/* (JEDEC standard commands ?)          */
-#define FLASH_BTYPE	0x0001		/* mask for bottom boot sector type	*/
+#define FLASH_BTYPE	0x0001	/* mask for bottom boot sector type     */
/*-----------------------------------------------------------------------
   * Timeout constants:
@@ -498,8 +498,8 @@ extern flash_info_t *flash_get_info(ulon
   * We can't find any specifications for maximum chip erase times,
   * so these values are guestimates.
   */
-#define FLASH_ERASE_TIMEOUT	120000	/* timeout for erasing in ms		*/
-#define FLASH_WRITE_TIMEOUT	500	/* timeout for writes  in ms		*/
+#define FLASH_ERASE_TIMEOUT	120000	/* timeout for erasing in ms            */
+#define FLASH_WRITE_TIMEOUT	500	/* timeout for writes  in ms            */
#endif /* !CONFIG_SYS_NO_FLASH */

    