For the silicon which doesn't have ROM support in QE, it always needs to load a pre-built ucode binary to IRAM so that QE can work.
Signed-off-by: Haiying Wang Haiying.Wang@freescale.com Signed-off-by: Hillel Avni Hillel.Avni@freescale.com --- drivers/qe/qe.c | 9 +++++++++ drivers/qe/qe.h | 1 + 2 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index e90a4a5..ea5a14b 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -161,6 +161,15 @@ void qe_init(uint qe_base) /* Init the QE IMMR base */ qe_immr = (qe_map_t *)qe_base;
+#ifdef CONFIG_SYS_QE_FW_ADDR + /* Upload microcode to IRAM for those SOCs which do not have ROM in QE. + */ + qe_upload_firmware((const struct qe_firmware *) CONFIG_SYS_QE_FW_ADDR); + + /* enable the microcode in IRAM */ + out_be32(&qe_immr->iram.iready,QE_IRAM_READY); +#endif + gd->mp_alloc_base = QE_DATAONLY_BASE; gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE;
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index a55555f..d78edba 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -230,6 +230,7 @@ typedef enum qe_clock { /* I-RAM */ #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ +#define QE_IRAM_READY 0x80000000
/* Structure that defines QE firmware binary files. *