We have been using locked cache for init_ram for MPC85xx for quite a long time. It works until e6500 comes. On e6500, L1 cache is write-through. L2 cache has to be enabled to hold the data. We have not locked L2 cache and we used reserved space in ccsr to make the address valid. Now the reserved address is no longer reserved, causing overlapping with SerDes module. The first patch changes the physical address of init_ram for e6500 and e5500 to another reserved space to avoid overlapping. The second patch locks L2 cache instead of L1 cache for e6500.
York Sun (2): powerpc: configs: Fix init_ram physical address for several boards powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram
arch/powerpc/cpu/mpc85xx/start.S | 10 +++++++++- include/configs/B4860QDS.h | 4 ++-- include/configs/T102xQDS.h | 4 ++-- include/configs/T102xRDB.h | 4 ++-- include/configs/T1040QDS.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/t4qds.h | 2 +- 10 files changed, 21 insertions(+), 13 deletions(-)