Hi all,
I'm just reading through the MPC8349EA-MDS-PB board start-up code to understand it, eg. the initial SRAM in data-cache trick.
In the BAT setups in include/configs/MPC8349EMDS.h, some of the CFG_IBAT settings include the bit setting BATL_MEMCOHERENCE, indicating that those BAT entries are setting the M bit in the WIMG field, where M = memory coherence.
I'm trying to understand why that bit is set. Here's what the documents I've looked at say:
According to the Programming Environments Manual, and Freescale AN1809 (minimal boot sequence app note), if the M bit is set, accesses cause the processor to 'indicate' the access via a hardware signal. No doubt this indication is so that another processor can maintain coherence.
The e300 core reference manual indicates that in real addressing mode, WIMG defaults to 0011b (p4-6), and the on p4-7 it says
'When the M attribute is set, and the access is performed, the global signal is asserted to indicate that the access is global.'
Then on p8-2 it shows that there is an e300 core gbl# signal that reflects the state of the M bit. Ok, so I can see what the hardware signal is that asserts based on the M setting.
But in an MPC8349E/EA is there anything monitoring the gbl# signal?
Chapter 7 of the MPC8349EA reference manual has an overview of the core, but it doesn't comment on the gbl# signal. There is a comment on p7-27 that
'the instruction cache is not snooped, and cache coherency must be maintained by software'
which I would interpret as meaning there ain't nobody listening on gbl# for instruction accesses. Then for the data caching, there is the comment on p7-29 that
'cache coherency is enforced by on-chip bus snooping logic'
But coherency with what? What other masters are there that the core has to be coherent with?
I can see that the coherent system bus (CSB) is a multi-master bus, and that the core is just another master on that bus. But I don't think any of these devices have a cache that they need to invalidate in response to the processor asserting its gbl# signal (p6-11 just shows request/grant, repeat, and priority signals to the arbiter).
So does anyone have an idea why the M bit would need to be set for the MPC8349EA BAT entries?
FYI: - The M-bit is set for the BAT entries for: DDR, PCI memory, SDRAM, stack-in-dcache, and Flash) - The M-bit is not set for: PCI I/O, IMMRs, and BCSRs these are cache inhibited and guarded.
Cheers, Dave
PS. This is the first time I've looked at the startup code of a processor with an MMU, or BATs, so if I've missed the obvious ... be kind :)