Hi Frank,Stefan,
Please see bleow error log for I am getting in detecting CFI flash chip. I am running u-boot from CRAM temporarily.
-------- U-Boot 2009.08 (Apr 01 2010 - 17:32:17) DRAM: 2 MB Top of RAM usable for U-Boot at: 00200000 Reserving 175k for U-Boot at: 001d4000 Reserving 1040k for malloc() at: 000d0000 Reserving 128 Bytes for Board Info at: 000cff80 Reserving 56 Bytes for Global Data at: 000cff48 Stack Pointer at: 000cff28 New Stack Pointer is: 000cff28 Now running in RAM - U-Boot at: 001d4000 FLASH: flash detect cfi fwc addr fc000000 cmd ff ff00 16bit x 8 bit fwc addr fc000000 cmd f0 f000 16bit x 8 bit fwc addr fc0000aa cmd 98 9800 16bit x 8 bit is= cmd 51(Q) addr fc000020 is= ffff 5100 fwc addr fc000aaa cmd 98 9800 16bit x 8 bit is= cmd 51(Q) addr fc000020 is= ffff 5100 fwc addr fc000000 cmd ff 0000 16bit x 16 bit fwc addr fc000000 cmd f0 0000 16bit x 16 bit fwc addr fc0000aa cmd 98 0000 16bit x 16 bit is= cmd 51(Q) addr fc000020 is= ffff 0000 fwc addr fc000aaa cmd 98 0000 16bit x 16 bit is= cmd 51(Q) addr fc000020 is= ffff 0000 fwc addr fc000000 cmd ff ff00ff00 32bit x 8 bit fwc addr fc000000 cmd f0 f000f000 32bit x 8 bit fwc addr fc000154 cmd 98 98009800 32bit x 8 bit is= cmd 51(Q) addr fc000040 is= ffffffff 51005100 fwc addr fc001554 cmd 98 98009800 32bit x 8 bit is= cmd 51(Q) addr fc000040 is= ffffffff 51005100 fwc addr fc000000 cmd ff 00000000 32bit x 16 bit fwc addr fc000000 cmd f0 00000000 32bit x 16 bit fwc addr fc000154 cmd 98 00000000 32bit x 16 bit is= cmd 51(Q) addr fc000040 is= ffffffff 00000000 fwc addr fc001554 cmd 98 00000000 32bit x 16 bit is= cmd 51(Q) addr fc000040 is= ffffffff 00000000 fwc addr fc000000 cmd ff 00000000 32bit x 32 bit fwc addr fc000000 cmd f0 00000000 32bit x 32 bit fwc addr fc000154 cmd 98 00000000 32bit x 32 bit is= cmd 51(Q) addr fc000040 is= ffffffff 00000000 fwc addr fc001554 cmd 98 00000000 32bit x 32 bit is= cmd 51(Q) addr fc000040 is= ffffffff 00000000 fwrite addr fc000000 cmd ff ff00ff00ff00ff00 64 bit x 8 bit fwrite addr fc000000 cmd f0 f000f000f000f000 64 bit x 8 bit fwrite addr fc0002a8 cmd 98 9800980098009800 64 bit x 8 bit is= cmd 51(Q) addr fc000080 is= ffffffffffffffff 5100510051005100 fwrite addr fc002aa8 cmd 98 9800980098009800 64 bit x 8 bit is= cmd 51(Q) addr fc000080 is= ffffffffffffffff 5100510051005100 fwrite addr fc000000 cmd ff 0000000000000000 64 bit x 16 bit fwrite addr fc000000 cmd f0 0000000000000000 64 bit x 16 bit fwrite addr fc0002a8 cmd 98 0000000000000000 64 bit x 16 bit is= cmd 51(Q) addr fc000080 is= ffffffffffffffff 0000000000000000 fwrite addr fc002aa8 cmd 98 0000000000000000 64 bit x 16 bit is= cmd 51(Q) addr fc000080 is= ffffffffffffffff 0000000000000000 fwrite addr fc000000 cmd ff 0000000000000000 64 bit x 32 bit fwrite addr fc000000 cmd f0 0000000000000000 64 bit x 32 bit fwrite addr fc0002a8 cmd 98 0000000000000000 64 bit x 32 bit is= cmd 51(Q) addr fc000080 is= ffffffffffffffff 0000000000000000 fwrite addr fc002aa8 cmd 98 0000000000000000 64 bit x 32 bit is= cmd 51(Q) addr fc000080 is= ffffffffffffffff 0000000000000000 fwrite addr fc000000 cmd ff 0000000000000000 64 bit x 64 bit fwrite addr fc000000 cmd f0 0000000000000000 64 bit x 64 bit fwrite addr fc0002a8 cmd 98 0000000000000000 64 bit x 64 bit is= cmd 51(Q) addr fc000080 is= ffffffffffffffff 0000000000000000 fwrite addr fc002aa8 cmd 98 0000000000000000 64 bit x 64 bit is= cmd 51(Q) addr fc000080 is= ffffffffffffffff 0000000000000000 not found ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB flash_protect ON: from 0xFFFC0000 to 0xFFFE81FF flash_protect ON: from 0xFFFA0000 to 0xFFFBFFFF *** failed *** ### ERROR ### Please RESET the board ###
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For slow devices, the memory controller is usually setup to use the GPCM.
Check your options and base registers
(OR0 and BR0).
What is GPCM? Which source/header file I need to check for these settings.?
You mention different size.. is the port size different too?
I think u-boot takes care of port size as if we do not define the port size then u-boot search with all possible port size. BTW how I can cross-check the port size?
For M29W128GH I have to do some code fixup from patch suggested by Stefan. Is there any special code fixup is required for S29GL512P flash chip support?
Thanks & Regards, Prakash
On Fri, Apr 9, 2010 at 6:57 PM, Frank Svendsbøe frank.svendsboe@gmail.comwrote:
I am using PPC440x5 Cpu core. How to check the chip-select flash is
using?
Earlier I have run the same code for M29W128GH and it works fine. But
with
S29GL512 it is not working. Now the difference is only in size and write/read timings. So I believe
it
should work in smooth manner.
Hmm.. If you're supposed to boot from this device, then I assume the flash is connected to CS0.For slow devices, the memory controller is usually setup to use the GPCM. Check your options and base registers (OR0 and BR0). Everything related to timing (for GPCM controlled devices) is done in these two registers.
If you have a BDI JTAG, you can set these registers using that and try to perform flash operations from here. Again, if you can, try to access the flash using the JTAG before experimenting with U-Boot.
You mention different size.. is the port size different too?
In order to help you, I think the community needs more info about your system. Stefan asked for logs, etc.
Regards, Frank