Re: [U-Boot] [PATCH v4 24/28] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10

On 01/10/2017 06:20 AM, Chee Tien Fong wrote:

From: Tien Fong Chee tien.fong.chee@intel.com

The drivers is restructured such common functions, gen5 functions. and arria10 functions are moved to misc.c, misc_gen5 and misc_arria10 respectively.

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@kernel.org Cc: Ching Liang See chin.liang.see@intel.com Cc: Tien Fong skywindctf@gmail.com

---

arch/arm/mach-socfpga/Makefile | 6 +- arch/arm/mach-socfpga/include/mach/misc.h | 32 ++ arch/arm/mach-socfpga/misc.c | 427 +------------------------- arch/arm/mach-socfpga/misc_arria10.c | 255 +++++++++++++++ arch/arm/mach-socfpga/{misc.c => misc_gen5.c} | 232 ++------------ 5 files changed, 337 insertions(+), 615 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h create mode 100644 arch/arm/mach-socfpga/misc_arria10.c copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (66%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index b8fcf6e..1ab68be 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -9,9 +9,11 @@

obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o board.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o \

• 		clock_manager_arria10.o pinmux.o
  

obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \

• 		reset_manager_gen5.o
  

• 		reset_manager_gen5.o misc_gen5.o \
  

• 		clock_manager_gen5.o
  
  

ifdef CONFIG_SPL_BUILD obj-y += spl.o diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h new file mode 100644 index 0000000..045268d --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -0,0 +1,32 @@ +/*

• • Copyright (C) 2016, Intel Corporation
• • SPDX-License-Identifier: GPL-2.0
• */

+#ifndef _MISC_H_ +#define _MISC_H_

Use tabs and spaces consistently.

+extern void dwmac_deassert_reset(const unsigned int of_reset_id,

• 		 const u32 phymode);
  

+struct bsel{

• const char *mode;
• const char *name;

+};

+extern struct bsel bsel_str[];

+#ifdef CONFIG_FPGA +extern void socfpga_fpga_add(void);

This MUST be declared in some header file, so there should be no need for any such crap like extern in C file.

+#else +inline void socfpga_fpga_add(void) {}

This should be fixed in some fpga.h or whereever this function comes from.

+#endif

This patch probably needs to be dispersed into the other A10 misc patches.

+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +unsigned int dedicated_uart_com_port(const void *blob); +unsigned int shared_uart_com_port(const void *blob); +unsigned int uart_com_port(const void *blob); +#endif

+#endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 510aa1d..7fd5c0e 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -1,5 +1,5 @@ /*

• • Copyright (C) 2012 Altera Corporation <www.altera.com>

• • Copyright (C) 2012-2016 Altera Corporation <www.altera.com>
  • SPDX-License-Identifier: GPL-2.0+
  */

@@ -7,45 +7,33 @@ #include <common.h> #include <asm/io.h> #include <errno.h> -#include <fdtdec.h> -#include <libfdt.h> #include <altera.h> #include <miiphy.h> #include <netdev.h> #include <watchdog.h> +#include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> -#include <asm/arch/scan_manager.h> #include <asm/arch/sdram_a10.h> #include <asm/arch/system_manager.h> #include <asm/arch/nic301.h> #include <asm/arch/scu.h> #include <asm/pl310.h>

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#include <dt-bindings/reset/altr,rst-mgr.h> -#else -#include <dt-bindings/reset/altr,rst-mgr-a10.h> -#endif

DECLARE_GLOBAL_DATA_PTR;

-static struct pl310_regs *const pl310 = +static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; -static struct socfpga_system_manager *sysmgr_regs =

• (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

-static struct socfpga_reset_manager *reset_manager_base =

• (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -static struct nic301_registers *nic301_regs =

• (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;

-#else -static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =

• (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;

-static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =

• (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;

-#endif -static struct scu_registers *scu_regs =

• (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;

+struct bsel bsel_str[] = {

• { "rsvd", "Reserved", },
• { "fpga", "FPGA (HPS2FPGA Bridge)", },
• { "nand", "NAND Flash (1.8V)", },
• { "nand", "NAND Flash (3.0V)", },
• { "sd", "SD/MMC External Transceiver (1.8V)", },
• { "sd", "SD/MMC Internal Transceiver (3.0V)", },
• { "qspi", "QSPI Flash (1.8V)", },
• { "qspi", "QSPI Flash (3.0V)", },

+};

int dram_init(void) { @@ -84,219 +72,6 @@ void v7_outer_cache_disable(void) clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); }

-/*

• • DesignWare Ethernet initialization
• */

-#ifdef CONFIG_ETH_DESIGNWARE -static void dwmac_deassert_reset(const unsigned int of_reset_id,

• 		 const u32 phymode)
  

-{

• u32 physhift, reset;
• if (of_reset_id == EMAC0_RESET) {

• physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
  

• reset = SOCFPGA_RESET(EMAC0);
  

• } else if (of_reset_id == EMAC1_RESET) {

• physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
  

• reset = SOCFPGA_RESET(EMAC1);
  

-#ifndef CONFIG_TARGET_SOCFPGA_GEN5

• } else if (of_reset_id == EMAC2_RESET) {

• reset = SOCFPGA_RESET(EMAC2);
  

-#endif

• } else {

• printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
  

• return;
  

• }

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)

• /* configure to PHY interface select choosed */
• clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,

• 	SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
  

• 	phymode << physhift);
  

-#else

• clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET],

• 	SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
  

• 	phymode);
  

-#endif

• /* Release the EMAC controller from reset */
• socfpga_per_reset(reset, 0);

-}

-static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) -{

• if (!phymode)

• return -EINVAL;
  

• if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {

• *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
  

• return 0;
  

• }
• if (!strcmp(phymode, "rgmii")) {

• *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
  

• return 0;
  

• }
• if (!strcmp(phymode, "rmii")) {

• *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
  

• return 0;
  

• }
• return -EINVAL;

-}

-static int socfpga_eth_reset(void) -{

• const void *fdt = gd->fdt_blob;
• struct fdtdec_phandle_args args;
• const char *phy_mode;
• u32 phy_modereg;
• int nodes[2]; /* Max. two GMACs */
• int ret, count;
• int i, node;
• /* Put both GMACs into RESET state. */
• socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
• socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
• count = fdtdec_find_aliases_for_id(fdt, "ethernet",

• 			   COMPAT_ALTERA_SOCFPGA_DWMAC,
  

• 			   nodes, ARRAY_SIZE(nodes));
  

• for (i = 0; i < count; i++) {

• node = nodes[i];
  

• if (node <= 0)
  

• 	continue;
  

• ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
  

• 				     "#reset-cells", 1, 0,
  

• 				     &args);
  

• if (ret || (args.args_count != 1)) {
  

• 	debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
  

• 	continue;
  

• }
  

• phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
  

• ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
  

• if (ret) {
  

• 	debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
  

• 	continue;
  

• }
  

• dwmac_deassert_reset(args.args[0], phy_modereg);
  

• }
• return 0;

-} -#else -static int socfpga_eth_reset(void) -{

• return 0;

-}; -#endif

-struct {

• const char *mode;
• const char *name;

-} bsel_str[] = {

• { "rsvd", "Reserved", },
• { "fpga", "FPGA (HPS2FPGA Bridge)", },
• { "nand", "NAND Flash (1.8V)", },
• { "nand", "NAND Flash (3.0V)", },
• { "sd", "SD/MMC External Transceiver (1.8V)", },
• { "sd", "SD/MMC Internal Transceiver (3.0V)", },
• { "qspi", "QSPI Flash (1.8V)", },
• { "qspi", "QSPI Flash (3.0V)", },

-};

-static const struct {

• const u16 pn;
• const char *name;
• const char *var;

-} const socfpga_fpga_model[] = {

• /* Cyclone V E */
• { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
• { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
• { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
• { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
• { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
• /* Cyclone V GX/GT */
• { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
• { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
• { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
• { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
• { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
• /* Cyclone V SE/SX/ST */
• { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
• { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
• { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
• { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
• /* Arria V */
• { 0x2d03, "Arria V, D5", "av_d5" },

-};

-static int socfpga_fpga_id(const bool print_id) -{

• const u32 altera_mi = 0x6e;
• const u32 id = scan_mgr_get_fpga_id();
• const u32 lsb = id & 0x00000001;
• const u32 mi = (id >> 1) & 0x000007ff;
• const u32 pn = (id >> 12) & 0x0000ffff;
• const u32 version = (id >> 28) & 0x0000000f;
• int i;
• if ((mi != altera_mi) || (lsb != 1)) {

• printf("FPGA:  Not Altera chip ID\n");
  

• return -EINVAL;
  

• }
• for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)

• if (pn == socfpga_fpga_model[i].pn)
  

• 	break;
  

• if (i == ARRAY_SIZE(socfpga_fpga_model)) {

• printf("FPGA:  Unknown Altera chip, ID 0x%08x\n", id);
  

• return -EINVAL;
  

• }
• if (print_id)

• printf("FPGA:  Altera %s, version 0x%01x\n",
  

•        socfpga_fpga_model[i].name, version);
  

• return i;

-}

-/*

• • Print CPU information
• */

-#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{

• const u32 bsel = (readl(&sysmgr_regs->bootinfo) >>

• 	  SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
  

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)

• puts("CPU: Altera SoCFPGA Platform\n");
• socfpga_fpga_id(1);

-#else

• puts("CPU: Altera SoCFPGA Arria 10\n");

-#endif

• printf("BOOT: %s\n", bsel_str[bsel].name);
• return 0;

-} -#endif

-#ifdef CONFIG_ARCH_MISC_INIT -int arch_misc_init(void) -{

• const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
• const int fpga_id = socfpga_fpga_id(0);
• setenv("bootmode", bsel_str[bsel].mode);
• if (fpga_id >= 0)

• setenv("fpgatype", socfpga_fpga_model[fpga_id].var);
  

• return socfpga_eth_reset();

-} -#endif

#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) int overwrite_console(void) @@ -327,15 +102,13 @@ static Altera_desc altera_fpga[] = { };

/* add device descriptor to FPGA device table */ -static void socfpga_fpga_add(void) +void socfpga_fpga_add(void) { int i; fpga_init(); for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) fpga_add(fpga_altera, &altera_fpga[i]); } -#else -static inline void socfpga_fpga_add(void) {} #endif

int arch_cpu_init(void) @@ -361,173 +134,3 @@ int arch_cpu_init(void)

return 0; }

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -/*

• • Convert all NIC-301 AMBA slaves from secure to non-secure
• */

-static void socfpga_nic301_slave_ns(void) -{

• writel(0x1, &nic301_regs->lwhps2fpgaregs);
• writel(0x1, &nic301_regs->hps2fpgaregs);
• writel(0x1, &nic301_regs->acp);
• writel(0x1, &nic301_regs->rom);
• writel(0x1, &nic301_regs->ocram);
• writel(0x1, &nic301_regs->sdrdata);

-}

-static uint32_t iswgrp_handoff[8];

-int arch_early_init_r(void) -{

• int i;
• /*

• * Write magic value into magic register to unlock support for
  

• * issuing warm reset. The ancient kernel code expects this
  

• * value to be written into the register by the bootloader, so
  

• * to support that old code, we write it here instead of in the
  

• * reset_cpu() function just before resetting the CPU.
  

• */
  

• writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
• for (i = 0; i < 8; i++) /* Cache initial SW setting regs */

• iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
  

• socfpga_bridges_reset(1);
• socfpga_nic301_slave_ns();
• /*

• * Private components security:
  

• * U-Boot : configure private timer, global timer and cpu component
  

• * access as non secure for kernel stage (as required by Linux)
  

• */
  

• setbits_le32(&scu_regs->sacr, 0xfff);
• /* Configure the L2 controller to make SDRAM start at 0 */

-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET

• writel(0x2, &nic301_regs->remap);

-#else

• writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
• writel(0x1, &pl310->pl310_addr_filter_start);

-#endif

• /* Add device descriptor to FPGA device table */
• socfpga_fpga_add();

-#ifdef CONFIG_DESIGNWARE_SPI

• /* Get Designware SPI controller out of reset */
• socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
• socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);

-#endif

-#ifdef CONFIG_NAND_DENALI

• socfpga_per_reset(SOCFPGA_RESET(NAND), 0);

-#endif

• return 0;

-}

-static void socfpga_sdram_apply_static_cfg(void) -{

• const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
• const uint32_t applymask = 0x8;
• uint32_t val = readl(staticcfg) | applymask;
• /*

• * SDRAM staticcfg register specific:
  

• * When applying the register setting, the CPU must not access
  

• * SDRAM. Luckily for us, we can abuse i-cache here to help us
  

• * circumvent the SDRAM access issue. The idea is to make sure
  

• * that the code is in one full i-cache line by branching past
  

• * it and back. Once it is in the i-cache, we execute the core
  

• * of the code and apply the register settings.
  

• *
  

• * The code below uses 7 instructions, while the Cortex-A9 has
  

• * 32-byte cachelines, thus the limit is 8 instructions total.
  

• */
  

• asm volatile(

• ".align	5			\n"
  

• "	b	2f		\n"
  

• "1:	str	%0,	[%1]	\n"
  

• "	dsb			\n"
  

• "	isb			\n"
  

• "	b	3f		\n"
  

• "2:	b	1b		\n"
  

• "3:	nop			\n"
  

• : : "r"(val), "r"(staticcfg) : "memory", "cc");

-}

-int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{

• if (argc != 2)

• return CMD_RET_USAGE;
  

• argv++;
• switch (*argv[0]) {
• case 'e': /* Enable */

• writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
  

• socfpga_sdram_apply_static_cfg();
  

• writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
  

• writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
  

• writel(iswgrp_handoff[1], &nic301_regs->remap);
  

• break;
  

• case 'd': /* Disable */

• writel(0, &sysmgr_regs->fpgaintfgrp_module);
  

• writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
  

• socfpga_sdram_apply_static_cfg();
  

• writel(0, &reset_manager_base->brg_mod_reset);
  

• writel(1, &nic301_regs->remap);
  

• break;
  

• default:

• return CMD_RET_USAGE;
  

• }
• return 0;

-} -#else -/* -+ * This function initializes security policies to be consistent across -+ * all logic units in the Arria 10. -+ * -+ * The idea is to set all security policies to be normal, nonsecure -+ * for all units. -+ */ -static void initialize_security_policies(void) -{

• /* Put OCRAM in non-secure */
• writel(0x003f0000, &noc_fw_ocram_base->region0);
• writel(0x1, &noc_fw_ocram_base->enable);
• /* Put DDR in non-secure */
• writel(0xffff0000, &noc_fw_ddr_l3_base->hpsregion0addr);
• writel(0x1, &noc_fw_ddr_l3_base->enable);

-}

-int arch_early_init_r(void) -{

• initialize_security_policies();
• /* Configure the L2 controller to make SDRAM start at 0 */
• writel(0x1, &pl310->pl310_addr_filter_start);
• /* assert reset to all except L4WD0 and L4TIMER0 */
• socfpga_per_reset_all();
• /* configuring the clock based on handoff */
• /* TODO: Add call to cm_basic_init() */
• /* Add device descriptor to FPGA device table */
• socfpga_fpga_add();
• return 0;

-} -#endif

-U_BOOT_CMD(

• bridge, 2, 1, do_bridge,
• "SoCFPGA HPS FPGA bridge control",
• "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
• "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
• ""

-); diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c new file mode 100644 index 0000000..6c50515 --- /dev/null +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -0,0 +1,255 @@ +/*

• • Copyright (C) 2016, Intel Corporation
• • SPDX-License-Identifier: GPL-2.0
• */

+#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <altera.h> +#include <miiphy.h> +#include <netdev.h> +#include <watchdog.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/sdram_a10.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/nic301.h> +#include <asm/pl310.h> +#include <fdtdec.h> +#include <ns16550.h>

+#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08 +#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58 +#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68 +#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18 +#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78 +#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98

+DECLARE_GLOBAL_DATA_PTR;

+static int find_peripheral_uart(const void *blob,

• int child, const char *node_name);

+static int is_peripheral_uart_true(const void *blob,

• int node, const char *child_name);

+static struct pl310_regs *const pl310 =

• (struct pl310_regs *)CONFIG_SYS_PL310_BASE;

+static struct socfpga_system_manager *sysmgr_regs =

• (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =

• (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;

+static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =

• (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;

+/*

• • DesignWare Ethernet initialization
• */

+#ifdef CONFIG_ETH_DESIGNWARE +void dwmac_deassert_reset(const unsigned int of_reset_id,

• 		 const u32 phymode)
  

+{

• u32 reset;
• if (of_reset_id == EMAC0_RESET) {

• reset = SOCFPGA_RESET(EMAC0);
  

• } else if (of_reset_id == EMAC1_RESET) {

• reset = SOCFPGA_RESET(EMAC1);
  

• } else if (of_reset_id == EMAC2_RESET) {

• reset = SOCFPGA_RESET(EMAC2);
  

• } else {

• printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
  

• return;
  

• }
• clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET],

• 	SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
  

• 	phymode);
  

• /* Release the EMAC controller from reset */
• socfpga_per_reset(reset, 0);

+} +#endif

+/* ++ * This function initializes security policies to be consistent across ++ * all logic units in the Arria 10. ++ * ++ * The idea is to set all security policies to be normal, nonsecure ++ * for all units. ++ */ +static void initialize_security_policies(void) +{

• /* Put OCRAM in non-secure */
• writel(0x003f0000, &noc_fw_ocram_base->region0);
• writel(0x1, &noc_fw_ocram_base->enable);
• /* Put DDR in non-secure */
• writel(0xffff0000, &noc_fw_ddr_l3_base->hpsregion0addr);
• writel(0x1, &noc_fw_ddr_l3_base->enable);

+}

+int arch_early_init_r(void) +{

• initialize_security_policies();
• /* Configure the L2 controller to make SDRAM start at 0 */
• writel(0x1, &pl310->pl310_addr_filter_start);
• /* assert reset to all except L4WD0 and L4TIMER0 */
• socfpga_per_reset_all();
• /* configuring the clock based on handoff */
• /* TODO: Add call to cm_basic_init() */
• /* Add device descriptor to FPGA device table */
• socfpga_fpga_add();
• return 0;

+}

+/*

• • This function looking the 1st encounter UART peripheral,
• • and then return its offset of the dedicated/shared IO pin
• • mux. offset value (zero and above).
• */

+static int find_peripheral_uart(const void *blob,

• int child, const char *node_name)

+{

• int len;
• fdt_addr_t base_addr = 0;
• fdt_size_t size;
• const u32 *cell;
• u32 value, offset = 0;
• base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
• if (base_addr != FDT_ADDR_T_NONE) {

• cell = fdt_getprop(blob, child, "pinctrl-single,pins",
  

• 	&len);
  

• if (cell != NULL) {
  

• 	for (; len > 0; len -= (2 * sizeof(u32))) {
  

• 		offset = fdt32_to_cpu(*cell++);
  

• 		value = fdt32_to_cpu(*cell++);
  

• 		/* Found UART peripheral */
  

• 		if (0x0D == value)
  

• 			return offset;
  

• 	}
  

• }
  

• }
• return -1;

+}

+/*

• • This function looking the 1st encounter UART peripheral,
• • and then return its offset of the dedicated/shared IO pin
• • mux. UART peripheral is found if the offset is not in negative
• • value.
• */

+static int is_peripheral_uart_true(const void *blob,

• int node, const char *child_name)

+{

• int child, len;
• const char *node_name;
• child = fdt_first_subnode(blob, node);
• if (child < 0)

• return -1;
  

• node_name = fdt_get_name(blob, child, &len);
• while (node_name) {

• if (!strcmp(child_name, node_name))
  

• 	return find_peripheral_uart(blob, child, node_name);
  

• child = fdt_next_subnode(blob, child);
  

• if (child < 0)
  

• 	break;
  

• node_name = fdt_get_name(blob, child, &len);
  

• }
• return -1;

+}

+/*

• • This function looking the 1st encounter UART dedicated IO peripheral,
• • and then return based address of the 1st encounter UART dedicated
• • IO peripheral.
• */

+unsigned int dedicated_uart_com_port(const void *blob) +{

• int node;
• node = fdtdec_next_compatible(blob, 0,

•  COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
  

• if (node < 0)

• return 0;
  

• if (0 <= is_peripheral_uart_true(blob, node, "dedicated"))

• return SOCFPGA_UART1_ADDRESS;
  

• else

• return 0;
  

+}

+/*

• • This function looking the 1st encounter UART shared IO peripheral, and then
• • return based address of the 1st encounter UART shared IO peripheral.
• */

+unsigned int shared_uart_com_port(const void *blob) +{

• int node, ret;
• node = fdtdec_next_compatible(blob, 0,

•  COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
  

• if (node < 0)

• return 0;
  

• ret = is_peripheral_uart_true(blob, node, "shared");
• if (PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 == ret ||

• PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 == ret ||
  

• PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 == ret)
  

• return SOCFPGA_UART0_ADDRESS;
  

• else if (PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 == ret ||

• PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 == ret ||
  

• PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 == ret)
  

• return SOCFPGA_UART1_ADDRESS;
  

• else

• return 0;
  

+}

+/*

• • This function looking the 1st encounter UART peripheral, and then return
• • base address of the 1st encounter UART peripheral.
• */

+unsigned int uart_com_port(const void *blob) +{

• unsigned int ret;
• ret = dedicated_uart_com_port(blob);
• if (ret)

• return ret;
  

• return shared_uart_com_port(blob);

+}

+/*

• • Print CPU information
• */

+#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{

• const u32 bsel = (readl(&sysmgr_regs->bootinfo) >>

• 	  SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
  

• puts("CPU: Altera SoCFPGA Arria 10\n");
• printf("BOOT: %s\n", bsel_str[bsel].name);
• return 0;

+} +#endif diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc_gen5.c similarity index 66% copy from arch/arm/mach-socfpga/misc.c copy to arch/arm/mach-socfpga/misc_gen5.c index 510aa1d..b91aeb1 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -1,7 +1,7 @@ /*

• • Copyright (C) 2012 Altera Corporation <www.altera.com>

• • Copyright (C) 2016, Intel Corporation

• • SPDX-License-Identifier: GPL-2.0+

• • SPDX-License-Identifier: GPL-2.0
  */

#include <common.h> @@ -13,6 +13,7 @@ #include <miiphy.h> #include <netdev.h> #include <watchdog.h> +#include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/scan_manager.h> #include <asm/arch/sdram_a10.h> @@ -20,12 +21,7 @@ #include <asm/arch/nic301.h> #include <asm/arch/scu.h> #include <asm/pl310.h>

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #include <dt-bindings/reset/altr,rst-mgr.h> -#else -#include <dt-bindings/reset/altr,rst-mgr-a10.h> -#endif

DECLARE_GLOBAL_DATA_PTR;

@@ -35,94 +31,47 @@ static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; static struct socfpga_reset_manager *reset_manager_base = (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -#else -static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =

• (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;

-static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =

• (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;

-#endif static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;

-int dram_init(void) -{

• gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
• return 0;

-}

-void enable_caches(void) -{ -#ifndef CONFIG_SYS_ICACHE_OFF

• icache_enable();

-#endif -#ifndef CONFIG_SYS_DCACHE_OFF

• dcache_enable();

-#endif -}

-void v7_outer_cache_enable(void) -{

• /* Disable the L2 cache */
• clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
• /* enable BRESP, instruction and data prefetch, full line of zeroes */
• setbits_le32(&pl310->pl310_aux_ctrl,

•      L310_AUX_CTRL_DATA_PREFETCH_MASK |
  

•      L310_AUX_CTRL_INST_PREFETCH_MASK |
  

•      L310_SHARED_ATT_OVERRIDE_ENABLE);
  

• /* Enable the L2 cache */
• setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);

-}

-void v7_outer_cache_disable(void) -{

• /* Disable the L2 cache */
• clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);

-}

/*

• DesignWare Ethernet initialization

*/ #ifdef CONFIG_ETH_DESIGNWARE -static void dwmac_deassert_reset(const unsigned int of_reset_id, +void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode) {

• u32 physhift, reset;

• u32 physhift;

• u32 reset;

  if (of_reset_id == EMAC0_RESET) { physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;

• reset = SOCFPGA_RESET(EMAC0); } else if (of_reset_id == EMAC1_RESET) { physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;

• reset = SOCFPGA_RESET(EMAC1);

-#ifndef CONFIG_TARGET_SOCFPGA_GEN5

• } else if (of_reset_id == EMAC2_RESET) {

• reset = SOCFPGA_RESET(EMAC2);
  

-#endif

• } else {

• }
• else { printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); return; }

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* configure to PHY interface select choosed */ clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl, SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, phymode << physhift); -#else

• clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET],

• 	SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
  

• 	phymode);
  

-#endif

/* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0); }

+/*

• • DesignWare Ethernet initialization
• */

static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) { if (!phymode) @@ -195,20 +144,6 @@ static int socfpga_eth_reset(void) }; #endif

-struct {

• const char *mode;
• const char *name;

-} bsel_str[] = {

• { "rsvd", "Reserved", },
• { "fpga", "FPGA (HPS2FPGA Bridge)", },
• { "nand", "NAND Flash (1.8V)", },
• { "nand", "NAND Flash (3.0V)", },
• { "sd", "SD/MMC External Transceiver (1.8V)", },
• { "sd", "SD/MMC Internal Transceiver (3.0V)", },
• { "qspi", "QSPI Flash (1.8V)", },
• { "qspi", "QSPI Flash (3.0V)", },

-};

static const struct { const u16 pn; const char *name; @@ -266,25 +201,6 @@ static int socfpga_fpga_id(const bool print_id) return i; }

-/*

• • Print CPU information
• */

-#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{

• const u32 bsel = (readl(&sysmgr_regs->bootinfo) >>

• 	  SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
  

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)

• puts("CPU: Altera SoCFPGA Platform\n");
• socfpga_fpga_id(1);

-#else

• puts("CPU: Altera SoCFPGA Arria 10\n");

-#endif

• printf("BOOT: %s\n", bsel_str[bsel].name);
• return 0;

-} -#endif

#ifdef CONFIG_ARCH_MISC_INIT int arch_misc_init(void) { @@ -297,72 +213,6 @@ int arch_misc_init(void) } #endif

-#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ -defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{

• return 0;

-} -#endif

-#ifdef CONFIG_FPGA -/*

• • FPGA programming support for SoC FPGA Cyclone V
• */

-static Altera_desc altera_fpga[] = {

• {

• /* Family */
  

• Altera_SoCFPGA,
  

• /* Interface type */
  

• fast_passive_parallel,
  

• /* No limitation as additional data will be ignored */
  

• -1,
  

• /* No device function table */
  

• NULL,
  

• /* Base interface address specified in driver */
  

• NULL,
  

• /* No cookie implementation */
  

• 0
  

• },

-};

-/* add device descriptor to FPGA device table */ -static void socfpga_fpga_add(void) -{

• int i;
• fpga_init();
• for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)

• fpga_add(fpga_altera, &altera_fpga[i]);
  

-} -#else -static inline void socfpga_fpga_add(void) {} -#endif

-int arch_cpu_init(void) -{ -#ifdef CONFIG_HW_WATCHDOG

• /*

• * In case the watchdog is enabled, make sure to (re-)configure it
  

• * so that the defined timeout is valid. Otherwise the SPL (Perloader)
  

• * timeout value is still active which might too short for Linux
  

• * booting.
  

• */
  

• hw_watchdog_init();

-#else

• /*

• * If the HW watchdog is NOT enabled, make sure it is not running,
  

• * for example because it was enabled in the preloader. This might
  

• * trigger a watchdog-triggered reboot of Linux kernel later.
  

• * Toggle watchdog reset, so watchdog in not running state.
  

• */
  

• socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
• socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);

-#endif

• return 0;

-}

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /*

• Convert all NIC-301 AMBA slaves from secure to non-secure

*/ @@ -387,7 +237,7 @@ int arch_early_init_r(void) * issuing warm reset. The ancient kernel code expects this * value to be written into the register by the bootloader, so * to support that old code, we write it here instead of in the

• * reset_cpu() function just before resetting the CPU.
  

• * reset_cpu() function just before reseting the CPU.
  

  */ writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);

@@ -486,43 +336,6 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])

return 0; } -#else -/* -+ * This function initializes security policies to be consistent across -+ * all logic units in the Arria 10. -+ * -+ * The idea is to set all security policies to be normal, nonsecure -+ * for all units. -+ */ -static void initialize_security_policies(void) -{

• /* Put OCRAM in non-secure */
• writel(0x003f0000, &noc_fw_ocram_base->region0);
• writel(0x1, &noc_fw_ocram_base->enable);
• /* Put DDR in non-secure */
• writel(0xffff0000, &noc_fw_ddr_l3_base->hpsregion0addr);
• writel(0x1, &noc_fw_ddr_l3_base->enable);

-}

-int arch_early_init_r(void) -{

• initialize_security_policies();
• /* Configure the L2 controller to make SDRAM start at 0 */
• writel(0x1, &pl310->pl310_addr_filter_start);
• /* assert reset to all except L4WD0 and L4TIMER0 */
• socfpga_per_reset_all();
• /* configuring the clock based on handoff */
• /* TODO: Add call to cm_basic_init() */
• /* Add device descriptor to FPGA device table */
• socfpga_fpga_add();
• return 0;

-} -#endif

U_BOOT_CMD( bridge, 2, 1, do_bridge, @@ -531,3 +344,20 @@ U_BOOT_CMD( "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" "" );

+/*

• • Print CPU information
• */

+#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{

• const u32 bsel = (readl(&sysmgr_regs->bootinfo) >>

• 	  SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
  

• puts("CPU: Altera SoCFPGA Platform\n");
• socfpga_fpga_id(1);
• printf("BOOT: %s\n", bsel_str[bsel].name);
• return 0;

+} +#endif