Samsung SoC use the cmu control to set clock.
Signed-off-by: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com --- drivers/mmc/s5p_sdhci.c | 3 +++ drivers/mmc/sdhci.c | 3 +++ include/configs/trats.h | 1 + include/sdhci.h | 2 ++ 4 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 9378e36..b978236 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -21,6 +21,7 @@ #include <malloc.h> #include <sdhci.h> #include <asm/arch/mmc.h> +#include <asm/arch/clk.h>
static char *S5P_NAME = "SAMSUNG SDHCI"; static void s5p_sdhci_set_control_reg(struct sdhci_host *host) @@ -87,6 +88,8 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width) host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
host->set_control_reg = &s5p_sdhci_set_control_reg; + host->set_clock = set_mmc_clk; + host->index = index;
host->host_caps = MMC_MODE_HC;
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 1709643..ac39e48 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -279,6 +279,9 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) } div >>= 1;
+ if (host->set_clock) + host->set_clock(host->index, div); + clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; diff --git a/include/configs/trats.h b/include/configs/trats.h index d2dfc9f..799658f 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -76,6 +76,7 @@ #define CONFIG_MMC #define CONFIG_S5P_SDHCI #define CONFIG_SDHCI +#define CONFIG_MMC_SDMA
/* PWM */ #define CONFIG_PWM diff --git a/include/sdhci.h b/include/sdhci.h index 9d37183..4351a62 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -248,8 +248,10 @@ struct sdhci_host { unsigned int clock; struct mmc *mmc; const struct sdhci_ops *ops; + int index;
void (*set_control_reg)(struct sdhci_host *host); + void (*set_clock)(int dev_index, unsigned int div); uint voltages; };