25 Aug
2014
25 Aug
'14
9:51 p.m.
On Monday, August 25, 2014 at 06:34:16 PM, Fabio Estevam wrote:
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
Acked-by: Marek Vasut marex@denx.de
Best regards, Marek Vasut