From 832783f2fab41fd9b937d56941ae0393298b548c Mon Sep 17 00:00:00 2001
From: liuhao <emb_hao@126.com>
Date: Fri, 27 Sep 2019 09:40:29 +0800
Subject: [PATCH] Request to submit the phytium platform to the uboot. Dear
 Maintainers: My name is Hao Liu, a software engineer from Phytium Technology
 Co., Ltd. We need to submit the phytium platform to the uboot Home. I hope
 that the Maintainers can approve with me. This soc is ft2004, and now this
 patch only support uart, pcie, usb, and gmac. I know that this patch has some
 problem, but I will make great efforts.

Signed-off-by: liuhao <liuhao@phytium.com.cn>
---
 MAINTAINERS                      |   7 ++
 arch/arm/Kconfig                 |   8 ++
 arch/arm/dts/Makefile            |   2 +
 arch/arm/dts/phytium-ft2004.dts  |  44 +++++++++
 board/phytium/ft2004/Kconfig     |  12 +++
 board/phytium/ft2004/MAINTAINERS |   8 ++
 board/phytium/ft2004/Makefile    |   9 ++
 board/phytium/ft2004/cpu.h       |  23 +++++
 board/phytium/ft2004/ft2004.c    | 111 ++++++++++++++++++++++
 configs/ft2004_defconfig         |  68 +++++++++++++
 drivers/pci/Kconfig              |   7 ++
 drivers/pci/Makefile             |   1 +
 drivers/pci/pcie_phytium.c       | 200 +++++++++++++++++++++++++++++++++++++++
 include/configs/ft2004.h         |  52 ++++++++++
 14 files changed, 552 insertions(+)
 create mode 100644 arch/arm/dts/phytium-ft2004.dts
 create mode 100644 board/phytium/ft2004/Kconfig
 create mode 100644 board/phytium/ft2004/MAINTAINERS
 create mode 100644 board/phytium/ft2004/Makefile
 create mode 100644 board/phytium/ft2004/cpu.h
 create mode 100644 board/phytium/ft2004/ft2004.c
 create mode 100644 configs/ft2004_defconfig
 create mode 100644 drivers/pci/pcie_phytium.c
 create mode 100644 include/configs/ft2004.h

diff --git a/MAINTAINERS b/MAINTAINERS
index bc67c49..1fa0aea 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -427,6 +427,13 @@ S:	Maintained
 T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-zynqmp-r5/
 
+ARM PHYTIUM
+M:	liuhao <liuhao@phytium.com.cn>
+M:	shuyiqi <shuyiqi@phytium.com.cn>
+S:	Maintained
+F:	drivers/pci/pcie_phytium.c
+F:	arch/arm/dts/phytium-ft2004.dts
+
 BINMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 51d4ace..cf18e2a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1044,6 +1044,13 @@ config TEGRA
 	imply DISTRO_DEFAULTS
 	imply FAT_WRITE
 
+config TARGET_FT2004
+	bool "Support Phytium FT2004 Platform"
+	select ARM64
+	help
+		Support for FT2004 platform.
+		It has 1GB Sdram, pcie, gmac, and usb.
+
 config TARGET_VEXPRESS64_AEMV8A
 	bool "Support vexpress_aemv8a"
 	select ARM64
@@ -1718,6 +1725,7 @@ source "arch/arm/cpu/armv8/Kconfig"
 
 source "arch/arm/mach-imx/Kconfig"
 
+source "board/phytium/ft2004/Kconfig"
 source "board/bosch/shc/Kconfig"
 source "board/bosch/guardian/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f553507..f2e3e53 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -14,6 +14,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
 	exynos4412-trats2.dtb \
 	exynos4412-odroid.dtb
 
+dtb-$(CONFIG_TARGET_FT2004) += phytium-ft2004.dtb
+
 dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb
 
 dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb
diff --git a/arch/arm/dts/phytium-ft2004.dts b/arch/arm/dts/phytium-ft2004.dts
new file mode 100644
index 0000000..d6ebad7
--- /dev/null
+++ b/arch/arm/dts/phytium-ft2004.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Phytium Ltd.
+ * shuyiqi  <shuyiqi@phytium.com.cn>
+ */
+
+/dts-v1/;
+
+/memreserve/	0x0000000080000000 0x0000000000100000;
+/ {
+	compatible = "phytium,ft2004";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	pcie-controller@40000000 {
+		compatible = "phytium,pcie-host-1.0";
+		device_type = "pci";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		reg = <0x0 0x40000000 0x0 0x10000000>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x1000000 0x0 0x0 0x0 0x50000000 0x0 0xF00000>,
+		<0x2000000 0x0 0x58000000 0x0 0x58000000 0x0 0x28000000>;
+	};
+
+	ethernet@2820c000 {
+		compatible = "st,stm32-dwmac";
+		reg = <0x0 0x2820C000 0x0 0x2000>;
+		phy-mode = "rgmii";
+	};
+
+	ethernet@28210000 {
+		compatible = "st,stm32-dwmac";
+		reg = <0x0 0x28210000 0x0 0x2000>;
+		phy-mode = "rgmii";
+	};
+
+	uart@28001000 {
+		compatible = "arm,pl011";
+		reg = <0x0 0x28001000 0x0 0x1000>;
+		clock = <48000000>;
+	};
+};
+
diff --git a/board/phytium/ft2004/Kconfig b/board/phytium/ft2004/Kconfig
new file mode 100644
index 0000000..865a609
--- /dev/null
+++ b/board/phytium/ft2004/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_FT2004
+
+config SYS_BOARD
+	default "ft2004"
+
+config SYS_VENDOR
+	default "phytium"
+
+config SYS_CONFIG_NAME
+	default "ft2004"
+
+endif
diff --git a/board/phytium/ft2004/MAINTAINERS b/board/phytium/ft2004/MAINTAINERS
new file mode 100644
index 0000000..6e4328b
--- /dev/null
+++ b/board/phytium/ft2004/MAINTAINERS
@@ -0,0 +1,8 @@
+PHYTIUM BOARD
+M:	liuhao <liuhao@phytium.com.cn>
+M:	shuyiqi <shuyiqi@phytium.com.cn>
+S:	Maintained
+F:	board/phytium/ft2004/*
+F:	include/configs/ft2004.h
+F:	configs/ft2004_defconfig
+
diff --git a/board/phytium/ft2004/Makefile b/board/phytium/ft2004/Makefile
new file mode 100644
index 0000000..948d523
--- /dev/null
+++ b/board/phytium/ft2004/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019
+# shuyiqi   <shuyiqi@phytium.com.cn>
+# liuhao	<liuhao@phytium.com.cn>
+#
+
+obj-y += ft2004.o
+
diff --git a/board/phytium/ft2004/cpu.h b/board/phytium/ft2004/cpu.h
new file mode 100644
index 0000000..3574a6b
--- /dev/null
+++ b/board/phytium/ft2004/cpu.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019
+ * Phytium Technology Ltd <www.phytium.com>
+ * shuyiqi <shuyiqi@phytium.com.cn>
+ */
+
+#ifndef _FT2004_CPU_H
+#define _FT2004_CPU_H
+
+/* FLUSH L3 CASHE */
+#define HNF_COUNT           0x8
+#define HNF_PSTATE_REQ      (HNF_BASE + 0x10)
+#define HNF_PSTATE_STAT     (HNF_BASE + 0x18)
+#define HNF_PSTATE_OFF      0x0
+#define HNF_PSTATE_SFONLY   0x1
+#define HNF_PSTATE_HALF     0x2
+#define HNF_PSTATE_FULL     0x3
+#define HNF_STRIDE          0x10000
+#define HNF_BASE		(unsigned long)(0x3A200000)
+
+#endif /* _FT2004_CPU_H */
+
diff --git a/board/phytium/ft2004/ft2004.c b/board/phytium/ft2004/ft2004.c
new file mode 100644
index 0000000..c7fb8d8
--- /dev/null
+++ b/board/phytium/ft2004/ft2004.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * shuyiqi <shuyiqi@phytium.com.cn>
+ * liuhao  <liuhao@phytium.com.cn>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <linux/arm-smccc.h>
+#include <linux/kernel.h>
+#include <scsi.h>
+#include "cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->mem_clk = 0;
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size =  PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	struct arm_smccc_res res;
+
+	printf("run in %s\n", __func__);
+	arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
+	printf("reset cpu error, %lx\n", res.a0);
+}
+
+static struct mm_region ft2004_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				 PTE_BLOCK_NON_SHARE |
+				 PTE_BLOCK_PXN |
+				 PTE_BLOCK_UXN
+	},
+	{
+		.virt = (u64)PHYS_SDRAM_1,
+		.phys = (u64)PHYS_SDRAM_1,
+		.size = (u64)PHYS_SDRAM_1_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				 PTE_BLOCK_NS |
+				 PTE_BLOCK_INNER_SHARE
+	},
+	{
+		0,
+	}
+};
+
+struct mm_region *mem_map = ft2004_mem_map;
+
+int print_cpuinfo(void)
+{
+	printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk);
+	return 0;
+}
+
+int __asm_flush_l3_dcache(void)
+{
+	int i, pstate;
+
+	for (i = 0; i < HNF_COUNT; i++)
+		writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
+	for (i = 0; i < HNF_COUNT; i++) {
+		do {
+			pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
+		} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
+	}
+
+	for (i = 0; i < HNF_COUNT; i++)
+		writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	int ret;
+
+	/* pci e */
+	pci_init();
+	/* scsi scan */
+	ret = scsi_scan(true);
+	if (ret) {
+		printf("scsi scan failed\n");
+		return CMD_RET_FAILURE;
+	}
+	return ret;
+}
+
diff --git a/configs/ft2004_defconfig b/configs/ft2004_defconfig
new file mode 100644
index 0000000..c26cd4b
--- /dev/null
+++ b/configs/ft2004_defconfig
@@ -0,0 +1,68 @@
+CONFIG_ARM=y
+CONFIG_ARM64=y
+CONFIG_TARGET_FT2004=y
+CONFIG_SYS_PROMPT="ft2004#"
+CONFIG_SYS_TEXT_BASE=0x88000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_AHCI=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_ARM_SMCCC=y
+
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw"
+
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
+CONFIG_DEFAULT_DEVICE_TREE="phytium-ft2004"
+CONFIG_DM=y
+
+CONFIG_CMD_PCI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_PHYTIUM=y
+
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_BOOTP=y
+CONFIG_CMD_TFTPBOOT=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_ETH_DESIGNWARE=y
+
+CONFIG_CMD_SCSI=y
+CONFIG_DOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_BLK=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB_STORAGE=y
+
+CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
+
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_MMC is not set
+# CONFIG_PSCI_RESET is not set
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 3fe38f7..9271b79 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -136,6 +136,13 @@ config PCIE_INTEL_FPGA
 	  Say Y here if you want to enable PCIe controller support on Intel
 	  FPGA, example Stratix 10.
 
+config PCI_PHYTIUM
+	bool "Phytium PCIe support"
+	depends on DM_PCI
+	help
+	  Say Y here if you want to enable PCIe controller support on
+	  Phytium SoCs.
+
 config PCI_MVEBU
 	bool "Enable Armada XP/38x PCIe driver"
 	depends on ARCH_MVEBU
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index b5ebd50..051e0c8 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -37,4 +37,5 @@ obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
 obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
 				pcie_layerscape_gen4_fixup.o
 obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
+obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
 obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
diff --git a/drivers/pci/pcie_phytium.c b/drivers/pci/pcie_phytium.c
new file mode 100644
index 0000000..92e281e
--- /dev/null
+++ b/drivers/pci/pcie_phytium.c
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium PCIE host driver
+ *
+ * Heavily based on drivers/pci/pcie_xilinx.c
+ *
+ * Copyright (C) 2019
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <asm/io.h>
+
+/**
+ * struct phytium_pcie - phytium PCIe controller state
+ * @cfg_base: The base address of memory mapped configuration space
+ */
+struct phytium_pcie {
+	void *cfg_base;
+};
+
+/*
+ * phytium_pci_skip_dev()
+ * @parent: Identifies the PCIe device to access
+ *
+ * Checks whether the parent of the PCIe device is bridge
+ *
+ * Return: true if it is bridge, else false.
+ */
+static int phytium_pci_skip_dev(pci_dev_t parent)
+{
+	unsigned char pos, id;
+	unsigned long addr = 0x40000000;
+	unsigned short capreg;
+	unsigned char port_type;
+
+	addr += PCI_BUS(parent) << 20;
+	addr += PCI_DEV(parent) << 15;
+	addr += PCI_FUNC(parent) << 12;
+
+	pos = 0x34;
+	while (1) {
+		pos = readb(addr + pos);
+		if (pos < 0x40)
+			break;
+		pos &= ~3;
+		id = readb(addr + pos);
+		if (id == 0xff)
+			break;
+		if (id == 0x10) {
+			capreg = readw(addr + pos + 2);
+			port_type = (capreg >> 4) & 0xf;
+			if (port_type == 0x6 || port_type == 0x4)
+				return 1;
+			else
+				return 0;
+		}
+		pos += 1;
+	}
+	return 0;
+}
+
+/**
+ * pci_phytium_conf_address() - Calculate the address of a config access
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @paddress: Pointer to the pointer to write the calculates address to
+ *
+ * Calculates the address that should be accessed to perform a PCIe
+ * configuration space access for a given device identified by the PCIe
+ * controller device @pcie and the bus, device & function numbers in @bdf. If
+ * access to the device is not valid then the function will return an error
+ * code. Otherwise the address to access will be written to the pointer pointed
+ * to by @paddress.
+ */
+static int pci_phytium_conf_address(struct udevice *bus, pci_dev_t bdf,
+				    uint offset,
+				    void **paddress)
+{
+	struct phytium_pcie *pcie = dev_get_priv(bus);
+	void *addr;
+	pci_dev_t bdf_parent;
+
+	unsigned int bus_no = PCI_BUS(bdf);
+	unsigned int dev_no = PCI_DEV(bdf);
+
+	bdf_parent = PCI_BDF((bus_no - 1), 0, 0);
+
+	addr = pcie->cfg_base;
+	addr += PCI_BUS(bdf) << 20;
+	addr += PCI_DEV(bdf) << 15;
+	addr += PCI_FUNC(bdf) << 12;
+
+	if (bus_no > 0 && dev_no > 0) {
+		if ((readb(addr + PCI_HEADER_TYPE) & 0x7f) !=
+				PCI_HEADER_TYPE_BRIDGE)
+			return -ENODEV;
+		if (phytium_pci_skip_dev(bdf_parent))
+			return -ENODEV;
+	}
+
+	addr += offset;
+	*paddress = addr;
+
+	return 0;
+}
+
+/**
+ * pci_phytium_read_config() - Read from configuration space
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @valuep: A pointer at which to store the read value
+ * @size: Indicates the size of access to perform
+ *
+ * Read a value of size @size from offset @offset within the configuration
+ * space of the device identified by the bus, device & function numbers in @bdf
+ * on the PCI bus @bus.
+ */
+static int pci_phytium_read_config(struct udevice *bus, pci_dev_t bdf,
+				   uint offset, ulong *valuep,
+				   enum pci_size_t size)
+{
+	return pci_generic_mmap_read_config(bus, pci_phytium_conf_address,
+					    bdf, offset, valuep, size);
+}
+
+/**
+ * pci_phytium_write_config() - Write to configuration space
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Write the value @value of size @size from offset @offset within the
+ * configuration space of the device identified by the bus, device & function
+ * numbers in @bdf on the PCI bus @bus.
+ */
+static int pci_phytium_write_config(struct udevice *bus, pci_dev_t bdf,
+				    uint offset, ulong value,
+				    enum pci_size_t size)
+{
+	return pci_generic_mmap_write_config(bus, pci_phytium_conf_address,
+					     bdf, offset, value, size);
+}
+
+/**
+ * pci_phytium_ofdata_to_platdata() - Translate from DT to device state
+ * @dev: A pointer to the device being operated on
+ *
+ * Translate relevant data from the device tree pertaining to device @dev into
+ * state that the driver will later make use of. This state is stored in the
+ * device's private data structure.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+static int pci_phytium_ofdata_to_platdata(struct udevice *dev)
+{
+	struct phytium_pcie *pcie = dev_get_priv(dev);
+	struct fdt_resource reg_res;
+
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int err;
+
+	err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
+			       0, &reg_res);
+	if (err < 0) {
+		pr_err("\"reg\" resource not found\n");
+		return err;
+	}
+
+	pcie->cfg_base = map_physmem(reg_res.start,
+				     fdt_resource_size(&reg_res),
+				     MAP_NOCACHE);
+
+	return 0;
+}
+
+static const struct dm_pci_ops pci_phytium_ops = {
+	.read_config	= pci_phytium_read_config,
+	.write_config	= pci_phytium_write_config,
+};
+
+static const struct udevice_id pci_phytium_ids[] = {
+	{ .compatible = "phytium,pcie-host-1.0" },
+	{ }
+};
+
+U_BOOT_DRIVER(pci_phytium) = {
+	.name			= "pci_phytium",
+	.id			= UCLASS_PCI,
+	.of_match		= pci_phytium_ids,
+	.ops			= &pci_phytium_ops,
+	.ofdata_to_platdata	= pci_phytium_ofdata_to_platdata,
+	.priv_auto_alloc_size	= sizeof(struct phytium_pcie),
+};
diff --git a/include/configs/ft2004.h b/include/configs/ft2004.h
new file mode 100644
index 0000000..ad9cf52
--- /dev/null
+++ b/include/configs/ft2004.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * shuyiqi  <shuyiqi@phytium.com.cn>
+ * liuhao   <liuhao@phytium.com.cn>
+ */
+
+#ifndef __FT_2004_CONFIG_H__
+#define __FT_2004_CONFIG_H__
+
+/* Sdram Bank #1 Address */
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_1_SIZE		0x7B000000
+#define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM_1
+
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x10000000)
+
+/* Size of Malloc Pool */
+#define CONFIG_ENV_SIZE 4096
+#define CONFIG_SYS_MALLOC_LEN	(1 * 1024 * 1024  + CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - 0x100000)
+
+/* PCI CONFIG */
+#define CONFIG_PCI_SCAN_SHOW
+
+/* SCSI */
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE 128
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SATA_MAX_DEVICE 4
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+
+/* BOOT */
+#define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"ethaddr=11:22:33:44:55:66\0"	\
+	"ipaddr=192.168.1.250\0"	\
+	"gatewayip=192.168.1.1\0"	\
+	"netmask=255.255.255.0\0"	\
+	"serverip=192.168.1.110\0"	\
+	"load_kernel=ext4load scsi 0:1 0x90100000 uImage-2004\0"	\
+	"load_fdt=ext4load scsi 0:1 0x95000000 ft2004-clock_64.dtb\0"\
+	"boot_fdt=bootm 0x90100000 -:- 0x95000000\0"	\
+	"distro_bootcmd=run load_kernel; run load_fdt; run boot_fdt"
+
+#endif
-- 
2.7.4

