This change allows to keep board description clean and minimalistic. This is especially helpful if one board may house different CPUs with different features.
It is applicable to both FPGA-based boards or those that have CPUs mounted on interchnagable daughter-boards.
Signed-off-by: Alexey Brodkin abrodkin@synopsys.com --- arch/arc/Kconfig | 19 +++++++++++++++++++ arch/arc/include/asm/cache.h | 13 +++++-------- arch/arc/lib/cache.c | 1 + configs/axs101_defconfig | 4 +++- configs/tb100_defconfig | 3 ++- include/configs/arcangel4-be.h | 1 - include/configs/arcangel4.h | 1 - include/configs/axs101.h | 4 ---- include/configs/tb100.h | 1 - 9 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index f7d2964..397b179 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -47,6 +47,25 @@ config ARC_MMU_V3
endchoice
+config SYS_ICACHE_OFF + bool "Do not use Instruction Cache" + default n + +config SYS_DCACHE_OFF + bool "Do not use Data Cache" + default n + +config ARC_CACHE_LINE_SHIFT + int "Cache Line Length (as power of 2)" + range 5 7 + default "6" + depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF + help + Starting with ARC700 4.9, Cache line length is configurable, + This option specifies "N", with Line-len = 2 power N + So line lengths of 32, 64, 128 are specified by 5,6,7, respectively + Linux only supports same line lengths for I and D caches. + choice prompt "Target select"
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 368d1f0..2725961 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -9,15 +9,12 @@
#include <config.h>
-/* - * The current upper bound for ARC L1 data cache line sizes is 128 bytes. - * We use that value for aligning DMA buffers unless the board config has - * specified an alternate cache line size. - */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#ifdef CONFIG_ARC_CACHE_LINE_SHIFT +#define CONFIG_SYS_CACHELINE_SIZE (1 << CONFIG_ARC_CACHE_LINE_SHIFT) +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE #else -#define ARCH_DMA_MINALIGN 128 +/* Satisfy users of ARCH_DMA_MINALIGN */ +#define ARCH_DMA_MINALIGN 128 #endif
#if defined(CONFIG_ARC_MMU_V2) diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index fa2a1e7..a227723 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -6,6 +6,7 @@
#include <config.h> #include <asm/arcregs.h> +#include <asm/cache.h>
/* Bit values in IC_CTRL */ #define IC_CTRL_CACHE_DISABLE (1 << 0) diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 5c0ca11..d165e41 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -1,3 +1,5 @@ CONFIG_ARC=y CONFIG_TARGET_AXS101=y -CONFIG_SYS_CLK_FREQ=750000000 \ No newline at end of file +CONFIG_SYS_CLK_FREQ=750000000 +CONFIG_ARC_CACHE_LINE_SHIFT=5 +CONFIG_SYS_DCACHE_OFF=y \ No newline at end of file diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig index d2de03b..e17a495 100644 --- a/configs/tb100_defconfig +++ b/configs/tb100_defconfig @@ -1,3 +1,4 @@ CONFIG_ARC=y CONFIG_TARGET_TB100=y -CONFIG_SYS_CLK_FREQ=500000000 \ No newline at end of file +CONFIG_SYS_CLK_FREQ=500000000 +CONFIG_ARC_CACHE_LINE_SHIFT=5 diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h index a43590b..b0bc8bc 100644 --- a/include/configs/arcangel4-be.h +++ b/include/configs/arcangel4-be.h @@ -11,7 +11,6 @@ * CPU configuration */ #define CONFIG_SYS_BIG_ENDIAN -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/* diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h index 565f70e..3268c56 100644 --- a/include/configs/arcangel4.h +++ b/include/configs/arcangel4.h @@ -10,7 +10,6 @@ /* * CPU configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/* diff --git a/include/configs/axs101.h b/include/configs/axs101.h index b94687c..ff3fad3 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -10,12 +10,8 @@ /* * CPU configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
-/* NAND controller DMA doesn't work correctly with D$ enabled */ -#define CONFIG_SYS_DCACHE_OFF - /* * Board configuration */ diff --git a/include/configs/tb100.h b/include/configs/tb100.h index f353950..32675c4 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -12,7 +12,6 @@ /* * CPU configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*