Segregate the FPGA Manager to support both GEN5 SoC and Stratix 10 SoC.
Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com --- arch/arm/mach-socfpga/fpga_manager.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach-socfpga/fpga_manager.c index 43fd2fe..a01e062 100644 --- a/arch/arm/mach-socfpga/fpga_manager.c +++ b/arch/arm/mach-socfpga/fpga_manager.c @@ -20,6 +20,8 @@ DECLARE_GLOBAL_DATA_PTR; /* Timeout count */ #define FPGA_TIMEOUT_CNT 0x1000000
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) + static struct socfpga_fpga_manager *fpgamgr_regs = (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
@@ -76,3 +78,5 @@ int fpgamgr_poll_fpga_ready(void)
return 0; } + +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */