At 00.33 26/11/2004, Roger Larsson wrote:
On Thursday 25 November 2004 19.42, llandre wrote:
I have a question about SDRAM detection code (cpu/ppc4xx/sdram.c). I tested it with the following configurations: Configuration #1: 32 MB (2 chips), SDRAM clk = 133 MHz Configuration #2: 32 MB (2 chips), SDRAM clk = 111 MHz and everything worked fine.
Then I tried the following: Configuration #3: 64 MB (2 chips), SDRAM clk = 111 MHz and the SDRAM does not work. U-Boot executes fine until it jumps to SDRAM after relocation. In this case, two chips K4S561632E-TI75 have been used. In my understanding the default value (0x07f00000) for the RTR register is wrong because these chips have a 64 ms/8k cycle refresh. Thus this register should be 0x03780000. I tried to change it but SDRAM did not work anyway. I suspect it is necessary to fix the TR register too or that the value for RTR is wrong. Any suggestions/remarks?
We are using the automatic SDRAM settings code (cpu/ppc4xx/sdp_sdram.c, unsure about exact name sdp_... Anyway I think you can use it for necessary calculations)
Have you configuread all four banks?
The processor (405EP) has just two banks. We use only the first one.
As you suggested I had a look at spd_sdram.c. In my understanding the settings used for RTR register in sdram.c are not correct. For SDRAM frequency = 133 MHz, this register is set as follows: rtr = 0x07f00000; Thus 0x07f0 * 1/133MHz = 2032 * 1/133MHz = 15.24 us this refresh is ok for 32 MB configuration (2 chips, 16 MB each).
For the 64 MB configuration (2 chips, 32 MB each) I think that this register should be set as follows: 64 ms / 8192 = 7.8 us 7.8 us * 133 MHz = 1040 = 0x410 => rtr = 0x04100000; Do you agree?
llandre
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