On Wednesday 24 September 2008, Adam Graham wrote:
These are the initial support files for the AMCC dual PPC460GT Arches reference board.
I suggest that you add a small description about this board this the commit log here.
Please find some comments below.
<snip>
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 1f27d78..fb19e0d 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -55,6 +55,14 @@ #endif
/*
- Only very few boards have default netdev not set to eth0 (like Arches)
- */
+#if !defined(CONFIG_NETDEV) +#define CONFIG_NETDEV eth0 +#endif
Nitpick: Don't add two empty lines please.
+/*
- Commands
*/ #include <config_cmd_default.h> @@ -147,9 +155,11 @@ /*
- Booting and default environment
*/ +#if !defined(CONFIG_PREBOOT) #define CONFIG_PREBOOT "echo;" \ "echo Type "run flash_nfs" to mount root filesystem over NFS;" \ "echo" +#endif #define CONFIG_BOOTCOMMAND "run flash_self"
/* @@ -184,7 +194,7 @@
- General common environment variables shared on all AMCC eval boards
*/ #define CONFIG_AMCC_DEF_ENV \
- "netdev=eth0\0" \
- "netdev=" xstr(CONFIG_NETDEV) "\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -197,8 +207,10 @@ "initrd_high=30000000\0" \ "kernel_addr_r=400000\0" \ "fdt_addr_r=800000\0" \
- "ramdisk_addr_r=C00000\0" \ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \ CONFIG_AMCC_DEF_ENV_ROOTPATH
/* @@ -214,6 +226,12 @@ "tftp ${fdt_addr_r} ${fdt_file}; " \ "run nfsargs addip addtty addmisc;" \ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${fdt_addr_r} ${fdt_file};" \"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \- "net_self=run net_self_load;" \
"run ramargs addip addtty addmisc;" \"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \/* diff --git a/include/configs/arches.h b/include/configs/arches.h new file mode 100644 index 0000000..6ad862f --- /dev/null +++ b/include/configs/arches.h @@ -0,0 +1,505 @@ +/*
- (C) Copyright 2008
- Adam Graham, Applied Micro Circuits Corp., agraham@amcc.com.
- Victor Gallardo, Applied Micro Circuits Corp., agraham@amcc.com.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+/************************************************************************
- arches.h - configuration for Arches (460GT)
- ***********************************************************************/
+#ifndef __CONFIG_H +#define __CONFIG_H
+/*-----------------------------------------------------------------------
- High Level Configuration Options
- *----------------------------------------------------------------------*/
+/* This config file is used for Arches (460GT) */ +#define CONFIG_ARCHES 1 /* Board is Arches */ +#define CONFIG_460GT 1 /* Specific PPC460GT */ +#define CONFIG_440 1 +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_NETDEV eth1
+/*
- Update default PREBOOT environment variables
- defined in amcc-common.h
- */
+#define CONFIG_PREBOOT \
- "setenv ethact ppc_4xx_eth1;" \
- "echo;" \
- "echo Type "run flash_nfs" to mount root filesystem over NFS;" \
- "echo;"
+/*
- Include common defines/options for all AMCC eval boards
- */
+#define CONFIG_HOSTNAME arches +#include "amcc-common.h"
+#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_TYPES 1 /* support board types */
+/*-----------------------------------------------------------------------
- RapidIO I/O and Registers
- *----------------------------------------------------------------------*/
+#define CONFIG_RAPIDIO +#define CFG_460GT_SRIO_ERRATA_1
+#define SRGPL0_REG_BAR 0x0000000DAA000000ull /* 16MB */ +#define SRGPL0_CFG_BAR 0x0000000DAB000000ull /* 16MB */ +#define SRGPL0_MNT_BAR 0x0000000DAC000000ull /* 16MB */ +#define SRGPL0_MSG_BAR 0x0000000DAD000000ull /* 16MB */ +#define SRGPL0_OUT_BAR 0x0000000DB0000000ull /* 256MB */
+#define CFG_SRGPL0_REG_BAR 0xAA000000 /* 16MB */ +#define CFG_SRGPL0_CFG_BAR 0xAB000000 /* 16MB */ +#define CFG_SRGPL0_MNT_BAR 0xAC000000 /* 16MB */ +#define CFG_SRGPL0_MSG_BAR 0xAD000000 /* 16MB */
+#define CFG_I2ODMA_BASE 0xCF000000 +#define CFG_I2ODMA_PHYS_ADDR 0x0000000400100000ull
+#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE +#undef CONFIG_PPC4XX_RAPIDIO_DEBUG +#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM +#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB +#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
+/* EBC stuff */ +#define CFG_NAND_ADDR 0xE0000000 +#define CFG_FPGA_BASE 0xE1000000 +#define CFG_CPLD_ADDR (CFG_FPGA_BASE + 0x00080000) +#define CFG_CPLD_DATA (CFG_FPGA_BASE + 0x00080002) +#define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */ +#define CFG_FLASH_BASE 0xFE000000 /* later mapped to this addr */ +#define CFG_FLASH_BASE_PHYS_H 0x4 +#define CFG_FLASH_BASE_PHYS_L 0xCE000000 +#define CFG_FLASH_BASE_PHYS (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \
(u64)CFG_FLASH_BASE_PHYS_L)+#define CFG_FLASH_SIZE (32 << 20)
+#define CFG_OCM_BASE 0xE3000000 /* OCM: 64k */ +#define CFG_OCM_PHYS_ADDR 0x0000000400040000ull
+#define CFG_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CFG_LOCAL_CONF_REGS 0xEF000000
+#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */
+#define CFG_AHB_BASE 0xE2000000 /* internal AHB peripherals */
+/*-----------------------------------------------------------------------
- Initial RAM & stack pointer (placed in OCM)
- *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+/*-----------------------------------------------------------------------
- Serial Port
- *----------------------------------------------------------------------*/
+#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
+/*-----------------------------------------------------------------------
- Environment
- *----------------------------------------------------------------------*/
+/*
- Define here the location of the environment variables (FLASH).
- */
+#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+/*-----------------------------------------------------------------------
- FLASH related
- *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector flinfo */ + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of 1 complete sector */ +#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */
+/*------------------------------------------------------------------------ ---- + * DDR SDRAM
*-------------------------------------------------------------------------- -*/ +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ + +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ +#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ +#undef CONFIG_PPC4xx_DDR_METHOD_A
+#define CFG_MBYTES_SDRAM 512
+/* DDR1/2 SDRAM Device Control Register Data Values */ +/* Memory Queue */ +#define CFG_SDRAM_R0BAS 0x0000f000 +#define CFG_SDRAM_R1BAS 0x00000000 +#define CFG_SDRAM_R2BAS 0x00000000 +#define CFG_SDRAM_R3BAS 0x00000000 +#define CFG_SDRAM_PLBADDULL 0x00000000 +#define CFG_SDRAM_PLBADDUHB 0x00000008 +#define CFG_SDRAM_CONF1LL 0x00001080 +#define CFG_SDRAM_CONF1HB 0x00001080 +#define CFG_SDRAM_CONFPATHB 0x10a68000
+/* SDRAM Controller */ +#define CFG_SDRAM0_MB0CF 0x00000701 +#define CFG_SDRAM0_MB1CF 0x00000000 +#define CFG_SDRAM0_MB2CF 0x00000000 +#define CFG_SDRAM0_MB3CF 0x00000000 +#define CFG_SDRAM0_MCOPT1 0x05322000 +#define CFG_SDRAM0_MCOPT2 0x00000000 +#define CFG_SDRAM0_MODT0 0x01000000 +#define CFG_SDRAM0_MODT1 0x00000000 +#define CFG_SDRAM0_MODT2 0x00000000 +#define CFG_SDRAM0_MODT3 0x00000000 +#define CFG_SDRAM0_CODT 0x00800021 +#define CFG_SDRAM0_RTR 0x06180000 +#define CFG_SDRAM0_INITPLR0 0xb5380000 +#define CFG_SDRAM0_INITPLR1 0x82100400 +#define CFG_SDRAM0_INITPLR2 0x80820000 +#define CFG_SDRAM0_INITPLR3 0x80830000 +#define CFG_SDRAM0_INITPLR4 0x80810040 +#define CFG_SDRAM0_INITPLR5 0x80800532 +#define CFG_SDRAM0_INITPLR6 0x82100400 +#define CFG_SDRAM0_INITPLR7 0x8a080000 +#define CFG_SDRAM0_INITPLR8 0x8a080000 +#define CFG_SDRAM0_INITPLR9 0x8a080000 +#define CFG_SDRAM0_INITPLR10 0x8a080000 +#define CFG_SDRAM0_INITPLR11 0x80000432 +#define CFG_SDRAM0_INITPLR12 0x808103c0 +#define CFG_SDRAM0_INITPLR13 0x80810040 +#define CFG_SDRAM0_INITPLR14 0x00000000 +#define CFG_SDRAM0_INITPLR15 0x00000000 +#define CFG_SDRAM0_RQDC 0x80000038 +#define CFG_SDRAM0_RFDC 0x00000257 +#define CFG_SDRAM0_RDCC 0x40000000 +#define CFG_SDRAM0_DLCR 0x03000091 +#define CFG_SDRAM0_CLKTR 0x40000000 +#define CFG_SDRAM0_WRDTR 0x82000823 +#define CFG_SDRAM0_SDTR1 0x80201000 +#define CFG_SDRAM0_SDTR2 0x42204243 +#define CFG_SDRAM0_SDTR3 0x090c0d1a +#define CFG_SDRAM0_MMODE 0x00000432 +#define CFG_SDRAM0_MEMODE 0x00000004
+/*-----------------------------------------------------------------------
- I2C
- *----------------------------------------------------------------------*/
+#define CFG_I2C_SPEED 400000 /* I2C speed */
+#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CFG_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */ +#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3
+/*-----------------------------------------------------------------------
- Ethernet
- *----------------------------------------------------------------------*/
+#define CONFIG_FIXED_PHY 0xFFFFFFFF +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_PHY_ADDR CONFIG_FIXED_PHY +#define CONFIG_PHY1_ADDR 0 +#define CONFIG_PHY2_ADDR 1 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2
+#define CFG_FIXED_PHY_PORT(devnum, speed, duplex) \
{devnum, speed, duplex},+#define CFG_FIXED_PHY_PORTS \
CFG_FIXED_PHY_PORT(0, 1000, FULL) \+#define CONFIG_M88E1112_PHY +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_DYNAMIC_ANEG 1
+/*
- The following PHY addresses 0xB,0xC,0xD are reserved
- in M88E1112 so use these for GPCS PHY addresses
- */
+#define CONFIG_GPCS_PHY_ADDR 0xB +#define CONFIG_GPCS_PHY1_ADDR 0xC +#define CONFIG_GPCS_PHY2_ADDR 0xD
+/*
- Default environment variables
- */
+#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fe000000\0" \
- "fdt_addr=fe1e0000\0" \
- "ramdisk_addr=fe200000\0" \
- "pciconfighost=1\0" \
- "pcie_mode=RP:RP\0" \
- ""
+/*
- Commands additional to the ones defined in amcc-common.h
- */
+#define CONFIG_CMD_DTT +#define CONFIG_CMD_PCI
+/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION
+/*-----------------------------------------------------------------------
- PCI stuff
- *----------------------------------------------------------------------*/
+/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+/* Board-specific PCI */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ +#undef CFG_PCI_MASTER_INIT
+#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+/*-----------------------------------------------------------------------
- Base addresses -- Note these are effective addresses where the
- actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
+#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest inc for PCIe port */ +#define CFG_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
+#define CFG_PCIE0_CFGBASE 0xc0000000 +#define CFG_PCIE1_CFGBASE 0xc1000000 +#define CFG_PCIE0_XCFGBASE 0xc3000000 +#define CFG_PCIE1_XCFGBASE 0xc3001000
+#define CFG_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
+/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
+/*-----------------------------------------------------------------------
- External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
+/*
- Arches has 32MBytes of NOR FLASH (Spansion 29GL256), but the
- boot EBC mapping only supports a maximum of 16MBytes
- (4.ff00.0000 - 4.ffff.ffff).
- To solve this problem, the FLASH has to get remapped to another
- EBC address which accepts bigger regions:
- 0xfe00.0000 -> 4.ce00.0000
- */
+/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x10055e00 +#define CFG_EBC_PB0CR (CFG_BOOT_BASE_ADDR | 0x9a000)
+/* Memory Bank 1 (FPGA) initialization */ +#define CFG_EBC_PB1AP 0x7f8ffe80 +#define CFG_EBC_PB1CR (CFG_FPGA_BASE | 0x3a000) +/* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
+#define CFG_EBC_CFG 0xB8400000 /* EBC0_CFG */
+/*
- PPC4xx GPIO Configuration
- */
+/* 460GT: Use EMAC2+3 configuration */ +#define CFG_4xx_GPIO_TABLE { \ +/* Out GPIO Alternate1 Alternate2 Alternate3 */ \
- { \
- /* GPIO Core 0 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \/* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
You wrapped the line here. I know that the original CFG_4xx_GPIO_TABLE implementation on some other boards uses too longs lines. But it makes the code better readable this way. So I think it makes sense to break the 80 chars per line rule in this case.
Best regards, Stefan
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