Device tree for Stratix10 SoC
Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/socfpga_stratix10_socdk.dts | 282 ++++++++++++++++++++++++++++++ 2 files changed, 284 insertions(+), 1 deletions(-) create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 62fbf32..61df5af 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -193,7 +193,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ - socfpga_cyclone5_vining_fpga.dtb + socfpga_cyclone5_vining_fpga.dtb \ + socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts new file mode 100644 index 0000000..bcd34ac --- /dev/null +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +/dts-v1/; +#include "skeleton.dtsi" +#include <dt-bindings/reset/altr,rst-mgr-s10.h> + +/ { + model = "Intel SOCFPGA Stratix 10 SoC Development Kit"; + compatible = "altr,socfpga-stratix10", "altr,socfpga"; + + #address-cells = <2>; + #size-cells = <1>; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + ethernet0 = &gmac0; + spi0 = &qspi; + i2c0 = &i2c; + spi1 = &spim0; + spi2 = &spim1; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x0 0x80000000>; /* 2GB */ + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + intc: intc@fffc1000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0xfffc1000 0x1000>, + <0x0 0xfffc2000 0x2000>, + <0x0 0xfffc4000 0x2000>, + <0x0 0xfffc6000 0x2000>; + }; + + soc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + ranges; + u-boot,dm-pre-reloc; + + rst: rstmgr@ffd11000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0x0 0xffd11000 0x100>; + altr,modrst-offset = <0x20>; + }; + + gmac0: ethernet@ff800000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", + "snps,dwmac"; + reg = <0x0 0xff800000 0x2000>; + interrupts = <0 90 4>; + interrupt-names = "macirq"; + interrupt-parent = <&intc>; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + max-speed = <1000>; + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + status = "okay"; + }; + + mmc0: dwmmc0@0xff808000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0x0 0xff808000 0x1000>; + interrupts = <0 96 4>; + interrupt-parent = <&intc>; + num-slots = <1>; + broken-cd; + bus-width = <4>; + fifo-depth = <0x400>; + cap-mmc-highspeed; + cap-sd-highspeed; + drvsel = <3>; + smplsel = <0>; + status = "okay"; + u-boot,dm-pre-reloc; + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0xffc02000 0x1000>; + interrupts = <0 108 4>; + interrupt-parent = <&intc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "okay"; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0x0 0xffb00000 0xffff>; + interrupts = <0 93 4>; + interrupt-parent = <&intc>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "okay"; + }; + + qspi: spi@ff8d2000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cadence,qspi"; + reg = <0x0 0xff8d2000 0x100>, + <0x0 0xff900000 0x100000>; + interrupts = <0 98 4>; + interrupt-parent = <&intc>; + sram-size = <1024>; + bus-num = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + u-boot,dm-pre-reloc; + + flash0: n25q1024a@0 { + u-boot,dm-pre-reloc; + compatible = "stmicro,n25q1024a"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; + }; + + i2c: i2c@ffc02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0xffc02900 0x100>; + interrupts = <0 104 0x4>; + interrupt-parent = <&intc>; + status = "okay"; + }; + + gpio0: gpio@ffc03200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0xffc03200 0x100>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + bank-name = "porta"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 110 4>; + interrupt-parent = <&intc>; + }; + }; + + gpio1: gpio@ffc03300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0xffc03300 0x100>; + status = "okay"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + bank-name = "portb"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 111 4>; + interrupt-parent = <&intc>; + }; + }; + + spim0: spi@ffda4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-ssi"; + reg = <0x0 0xffda4000 0x1000>; + interrupts = <0 99 4>; + interrupt-parent = <&intc>; + num-cs = <1>; + bus-num = <0>; + spi-max-frequency = <25000000>; + status = "okay"; + }; + + spim1: spi@ffda5000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-ssi"; + reg = <0x0 0xffda5000 0x1000>; + interrupts = <0 100 4>; + interrupt-parent = <&intc>; + num-cs = <1>; + bus-num = <0>; + spi-max-frequency = <25000000>; + status = "disabled"; + }; + }; +};