On Wed, Mar 14, 2018 at 08:36:30PM -0500, David Lechner wrote:
commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency") changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP block. However, in doing so, it caused the PLLOUT clock to be outside of the allowable specifications given in the OMAP-L138 data sheet. (It says PLLOUT must be 600MHz max). It also uses a PLLM value outside of the range given in the TRM (it says PLLM must in the range 0 to 0x1f).
So here is what we have currently:
PLLOUT = 24 / (0 + 1) * (37 + 1) = 912MHz (out of spec) ^ ^ ^ CLKIN PREDIV PLLM (out of spec)
input to PLLDIVn = 912 / (1 + 1) = 456MHz (desired result) ^ ^ PLLOUT POSTDIV
This changes the PLLM value to 18 and the POSTDIV value to 0 so that PLLOUT is now within specification but we still get the desired result.
PLLOUT = 24 / (0 + 1) * (18 + 1) = 456MHz (within spec) ^ ^ ^ CLKIN PREDIV PLLM
input to PLLDIVn = 456 / (0 + 1) = 456MHz (desired result) ^ ^ PLLOUT POSTDIV
Fixes: 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency") Signed-off-by: David Lechner david@lechnology.com Reported-by: Sekhar Nori nsekhar@ti.com Tested-by: Sekhar Nori nsekhar@ti.com
Applied to u-boot/master, thanks!