Amlogic SM1 SoCs doesn't handle very well high clocks from the DIV2 input Thus we limit the max freq to 26MHz on SM1 SoCs until we handle higher frequencies via the first input from a composite clock.
Here 26MHz corresponds to MMC_HS clock speed.
We also add a u-boot only sm1 compatible to distinguish the controller in a new meson-sm1-u-boot.dtsi and reworks the other -u-boot.dtsi to use this for SM1 based boards.
Finally a TOFIX is added to precise the clock management should use the clock controller instead of local management with fixed clock rates.
Neil Armstrong (3): mmc: meson-gx: move arch header to local header mmc: meson-gx: limit max frequency on SM1 SoCs ARM: dts: meson-sm1: add u-boot specific MMC controller compatible
.../meson-g12b-a311d-khadas-vim3-u-boot.dtsi | 1 + arch/arm/dts/meson-khadas-vim3-u-boot.dtsi | 2 -- .../dts/meson-sm1-khadas-vim3l-u-boot.dtsi | 1 + arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi | 2 +- arch/arm/dts/meson-sm1-sei610-u-boot.dtsi | 2 +- arch/arm/dts/meson-sm1-u-boot.dtsi | 20 +++++++++++++ drivers/mmc/meson_gx_mmc.c | 28 ++++++++++++++++--- .../sd_emmc.h => drivers/mmc/meson_gx_mmc.h | 10 ++++--- 8 files changed, 54 insertions(+), 12 deletions(-) create mode 100644 arch/arm/dts/meson-sm1-u-boot.dtsi rename arch/arm/include/asm/arch-meson/sd_emmc.h => drivers/mmc/meson_gx_mmc.h (95%)