Code has been changed to do not use DMA anymore with the NAND controller, instead PIO is used. Then, DMA-specific initialization may be dropped.
Signed-off-by: Miquel Raynal miquel.raynal@bootlin.com --- board/sunxi/board.c | 5 ----- 1 file changed, 5 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 54ac018b80..59cfddc8e0 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -287,11 +287,6 @@ static void nand_clock_setup(void)
setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); -#ifdef CONFIG_MACH_SUN9I - setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); -#else - setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); -#endif setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); }