Sometimes it's helpful to know the reset reason caused in the SoC. Add reset reason detection for the RK3288 SoC. This will set an environemt variable which represents the reset reason.
Signed-off-by: Wadim Egorov w.egorov@phytec.de Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
--- Changes in v2: - Added Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com - Clear cru_glb_rst_st - POR if cru_glb_rst_st is 0 - RST if 1st or 2nd bit is set Can be tested with mw 0xff7601b0 0xfffffdb9 mw 0xff7601b4 0xffffeca8
--- arch/arm/mach-rockchip/rk3288-board.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 613967c..da1995c 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -11,6 +11,7 @@ #include <syscon.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/cru_rk3288.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3288.h> #include <asm/arch/qos_rk3288.h> @@ -70,10 +71,44 @@ int rk3288_qos_init(void) return 0; }
+static void rk3288_detect_reset_reason(void) +{ + struct rk3288_cru *cru = rockchip_get_cru(); + if (IS_ERR(cru)) + return; + + switch (cru->cru_glb_rst_st) { + case 0: + setenv("reset_reason", "POR"); + break; + case (1 << 0): + case (1 << 1): + setenv("reset_reason", "RST"); + break; + case (1 << 2): + case (1 << 3): + setenv("reset_reason", "THERMAL"); + break; + case (1 << 4): + case (1 << 5): + setenv("reset_reason", "WDOG"); + break; + default: + setenv("reset_reason", "unknown reset"); + } + + /* + * Clear cru_glb_rst_st, so we can determine the last reset cause + * for following resets. + */ + rk_clrreg(&cru->cru_glb_rst_st, 0x3f); +} + int board_late_init(void) { setup_boot_mode(); rk3288_qos_init(); + rk3288_detect_reset_reason();
return rk_board_late_init(); }