Bit mirroring might not be needed in slave serial mode, but is needed in slave parallel mode. Bytes in the .bit file are stored with the LSB on the
left
side. The bytes must then be reversed before being written in slave
parallel
mode, as the FPGA expects the LSB on D0, not on D7.
Again, it depends on the processor you are using and how it's hooked up to the FPGA. BTW, according to the Spartan 3 data sheet "data bit D0 is the MOST-significant (msb) bit and D7 is the least-significant bit (lsb)" (pg 167, Xilinx UG332 Spartan-3 Generation confiuration User Guide). Maybe you are refering to a different FPGA?
Without mirroring, bitstreams won't load in slave parallel mode. You
should
keep mirroring, and change the slave serial code to shift bits the other
way
around.
I must respectfully disagree. In my design, if I mirror in the code the FPGA does NOT load. In a PPC, D0 is the MSB, NOT the LSB. In a Spartan 3 FPGA, D0 is the MSB, NOT the LSB. Therefore if you connect your bus straight across between the PPC and the Spartan 3 FPGA, AND do mirroring in the code, your FPGA will not load.
Bruce