In every sub directory, Makefile is like follows:
include $(TOPDIR)/config.mk
LIB = $(obj)libfoo.o
COBJS := ... COBJS += ... SOBJS := ...
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
Top and bottom parts are common in almost all sub-makefiles. This is a big waste. This commit pushes common parts of makefiles into script/Makefile.build.
Going forward sub-makefiles only need to describe this part:
COBJS := ... COBJS += ... SOBJS := ...
But, script/Makefile.build includes the glue code to support obj-y, the following style (the same as Kbuild) is preferable:
obj-y := ... obj-$(CONFIG_FOO) += ... obj-$(CONFIG_BAR) += ...
The conventional (non-Kbuild) Makefile style is still supported. This is achieved by greping the Makefile before entering into it. U-Boot conventional sub makefiles always include some other makefiles. So the build system searches a line beginning with "include" keyword in the makefile in order to distinguish which style it is. If the Makefile include a "include" line, we assume it is a conventional U-Boot style. Otherwise, it is treated as a Kbuild-style makefile.
(At first, I tried to grep "rules.mk" keyword instead, but I found it does not work. Almost all sub makefiles include "rules.mk", but there exist three exception: - board/avnet/fx12mm/Makefile - board/avnet/v5fx30teval/Makefile - board/xilinx/ml507/Makefile These three makefiles include "rules.mk" indirectly. Anyway, they look weird, so they should be fixed lator.)
With this tweak, we can switch sub-makefiles from U-Boot style to Kbuild style little by little.
This refactoring of sub makefiles is the first step towards Kbuild, and makes it easy to import a "real" Kbuild from Linux Kernel.
Note that this refactoring breaks nothing because it just moves the common parts into scripts/Makefile.build.
Note one more thing:
obj-y := foo/ # descending into foo sub directory
syntax is not supported yet. (This feature will be implemented in the upcoming commit.)
Of course, scripts/Makefile.build added by this commit is temporary. It shall be replaced with the one of Linux Kernel in future.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Simon Glass sjg@chromium.org Cc: Tom Rini trini@ti.com ---
Changes for v2: - fix commit log (purely cosmetic)
Makefile | 34 ++++++++++++++++++++++++++++++---- scripts/Makefile.build | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ spl/Makefile | 20 ++++++++++++++++++-- 3 files changed, 96 insertions(+), 6 deletions(-) create mode 100644 scripts/Makefile.build
diff --git a/Makefile b/Makefile index 07abef4..36bbd09 100644 --- a/Makefile +++ b/Makefile @@ -593,14 +593,35 @@ ifeq ($(CONFIG_KALLSYMS),y) $(GEN_UBOOT) $(obj)common/system_map.o endif
+# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles +# U-Boot conventional sub makefiles always include some other makefiles. +# So, the build system searches a line beginning with "include" before entering into the sub makefile +# in order to distinguish which style it is. +# If the Makefile include a "include" line, we assume it is an U-Boot style makefile. +# Otherwise, it is treated as a Kbuild-style makefile. + +# We do not need to build $(OBJS) explicitly. +# It is built while we are at $(CPUDIR)/lib$(CPU).o build. $(OBJS): depend - $(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@)) + if grep -q "^include" $(CPUDIR)/Makefile; then \ + $(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@)); \ + fi
$(LIBS): depend $(SUBDIR_TOOLS) - $(MAKE) -C $(dir $(subst $(obj),,$@)) + if grep -q "^include" $(dir $(subst $(obj),,$@))Makefile; then \ + $(MAKE) -C $(dir $(subst $(obj),,$@)); \ + else \ + $(MAKE) -C $(dir $(subst $(obj),,$@)) -f $(TOPDIR)/scripts/Makefile.build; \ + mv $(dir $@)built-in.o $@; \ + fi
$(LIBBOARD): depend $(LIBS) - $(MAKE) -C $(dir $(subst $(obj),,$@)) + if grep -q "^include" $(dir $(subst $(obj),,$@))/Makefile; then \ + $(MAKE) -C $(dir $(subst $(obj),,$@)); \ + else \ + $(MAKE) -C $(dir $(subst $(obj),,$@)) -f $(TOPDIR)/scripts/Makefile.build; \ + mv $(dir $@)built-in.o $@; \ + fi
$(SUBDIRS): depend $(MAKE) -C $@ all @@ -637,7 +658,12 @@ depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \ $(obj)include/generated/generic-asm-offsets.h \ $(obj)include/generated/asm-offsets.h for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \ - $(MAKE) -C $$dir _depend ; done + if grep -q "^include" $$dir/Makefile; then \ + $(MAKE) -C $$dir _depend ; \ + else \ + $(MAKE) -C $$dir -f $(TOPDIR)/scripts/Makefile.build _depend; \ + fi; \ + done
TAG_SUBDIRS = $(SUBDIRS) TAG_SUBDIRS += $(dir $(__LIBS)) diff --git a/scripts/Makefile.build b/scripts/Makefile.build new file mode 100644 index 0000000..f969ec5 --- /dev/null +++ b/scripts/Makefile.build @@ -0,0 +1,48 @@ +# our default target +.PHONY: all +all: + +include $(TOPDIR)/config.mk + +LIB := $(obj)built-in.o +LIBGCC = $(obj)libgcc.o +SRCS := + +include Makefile + +# Backward compatible: obj-y is preferable +COBJS := $(sort $(COBJS) $(COBJS-y)) +SOBJS := $(sort $(SOBJS) $(SOBJS-y)) + +# Going forward use the following +obj-y := $(sort $(obj-y)) +extra-y := $(sort $(extra-y)) +lib-y := $(sort $(lib-y)) + +SRCS += $(COBJS:.o=.c) $(SOBJS:.o=.S) \ + $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S)) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS) $(obj-y)) + +LGOBJS := $(addprefix $(obj),$(sort $(GLSOBJS) $(GLCOBJS)) $(lib-y)) + +all: $(LIB) $(addprefix $(obj),$(extra-y)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +ifneq ($(strip $(lib-y)),) +all: $(LIBGCC) + +$(LIBGCC): $(obj).depend $(LGOBJS) + $(call cmd_link_o_target, $(LGOBJS)) +endif + +######################################################################### + +# defines $(obj).depend target + +include $(TOPDIR)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/spl/Makefile b/spl/Makefile index 174d0a7..48f2c65 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -199,11 +199,27 @@ GEN_UBOOT = \ $(obj)$(SPL_BIN): depend $(START) $(LIBS) $(obj)u-boot-spl.lds $(GEN_UBOOT)
+# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles +# U-Boot conventional sub makefiles always include some other makefiles. +# So, the build system searches a line beginning with "include" before entering into the sub makefile +# in order to distinguish which style it is. +# If the Makefile include a "include" line, we assume it is an U-Boot style makefile. +# Otherwise, it is treated as a Kbuild-style makefile. + +# We do not need to build $(START) explicitly. +# It is built while we are at $(CPUDIR)/lib$(CPU).o build. $(START): depend - $(MAKE) -C $(SRCTREE)/$(START_PATH) $@ + if grep -q "^include" $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))Makefile; then \ + $(MAKE) -C $(SRCTREE)/$(START_PATH) $@; \ + fi
$(LIBS): depend - $(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)) + if grep -q "^include" $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))Makefile; then \ + $(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)); \ + else \ + $(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)) -f $(TOPDIR)/scripts/Makefile.build; \ + mv $(dir $@)built-in.o $@; \ + fi
$(obj)u-boot-spl.lds: $(LDSCRIPT) depend $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@