Re: [U-Boot] [PATCH 06/26] spi: mt7621-spi: restore default register value after each xfer

On 28.08.19 08:37, Weijie Gao wrote:

Currently this driver uses a different way to implement the spi xfer, by modifying some fields of two registers, which is incompatible with the MTK's original SDK linux driver. This will cause the flash data being damaged by the SDK driver.

This patch lets the mt7621_spi_set_cs() restore the original register fields after cs deactivated.

What is this "MTK's original SDK Linux driver"? It's not the mainline Linux SPI driver, correct? Which platforms / boards are using it?

Please note that in general, drivers in Linux should not make any assumptions about prior register setup. So the driver you are referring to should configure all registers correctly for its setup.

But I don't object to this patch, so if this is really needed for some of your customers, please go ahead:

Reviewed-by: Stefan Roese sr@denx.de

Thanks, Stefan

Signed-off-by: Weijie Gao weijie.gao@mediatek.com

drivers/spi/mt7621_spi.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/drivers/spi/mt7621_spi.c b/drivers/spi/mt7621_spi.c index 20fe93d416..06484e7abe 100644 --- a/drivers/spi/mt7621_spi.c +++ b/drivers/spi/mt7621_spi.c @@ -20,6 +20,10 @@ #define MT7621_SPI_TRANS 0x00 #define MT7621_SPI_TRANS_START BIT(8) #define MT7621_SPI_TRANS_BUSY BIT(16) +#define TRANS_ADDR_SZ GENMASK(20, 19) +#define TRANS_ADDR_SZ_SHIFT 19 +#define TRANS_MOSI_BCNT GENMASK(3, 0) +#define TRANS_MOSI_BCNT_SHIFT 0

#define MT7621_SPI_OPCODE 0x04 #define MT7621_SPI_DATA0 0x08 @@ -49,20 +53,22 @@ struct mt7621_spi { unsigned int sys_freq; };

-static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex) -{

• setbits_le32(rs->base + MT7621_SPI_MASTER,

•      MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
  

-}

• static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable) {
• u32 val = 0;
• debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable");
• if (enable)

• val = BIT(cs);
  

• iowrite32(val, rs->base + MT7621_SPI_POLAR);

• if (enable) {

• setbits_le32(rs->base + MT7621_SPI_MASTER,
  

• 	     MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
  

• iowrite32(BIT(cs), rs->base + MT7621_SPI_POLAR);
  

• } else {

• iowrite32(0, rs->base + MT7621_SPI_POLAR);
  

• iowrite32((2 << TRANS_ADDR_SZ_SHIFT) |
  

• 	  (1 << TRANS_MOSI_BCNT_SHIFT),
  

• 	  rs->base + MT7621_SPI_TRANS);
  

• clrbits_le32(rs->base + MT7621_SPI_MASTER,
  

• 	     MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
  

• } }

  static int mt7621_spi_set_mode(struct udevice *bus, uint mode)

@@ -267,8 +273,6 @@ static int mt7621_spi_probe(struct udevice *dev) return -EINVAL; }

• mt7621_spi_reset(rs, 0);
• return 0; }

Viele Grüße, Stefan