Factor out the code we use to actually write a tlb entry.
set_tlb is a logical view of the TLB while write_tlb is a low level matching the MAS registers.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- cpu/mpc85xx/start.S | 19 +++++++++++++++++++ cpu/mpc85xx/tlb.c | 12 +----------- include/asm-ppc/mmu.h | 2 ++ 3 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 7a23b4f..ea32659 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1127,6 +1127,25 @@ flush_dcache:
blr
+ .globl write_tlb +write_tlb: + mtspr MAS0,r3 + mtspr MAS1,r4 + mtspr MAS2,r5 + mtspr MAS3,r6 +#ifdef CONFIG_ENABLE_36BIT_PHYS + mtspr MAS7,r7 +#endif + li r3,0 +#ifdef CONFIG_SYS_BOOK3E_HV + mtspr MAS8,r3 +#endif + isync + tlbwe + msync + isync + blr + .globl setup_ivors setup_ivors:
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 03c2449..3e502ac 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -44,17 +44,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms); _mas7 = rpn >> 32;
- mtspr(MAS0, _mas0); - mtspr(MAS1, _mas1); - mtspr(MAS2, _mas2); - mtspr(MAS3, _mas3); -#ifdef CONFIG_ENABLE_36BIT_PHYS - mtspr(MAS7, _mas7); -#endif -#ifdef CONFIG_SYS_BOOK3E_HV - mtspr(MAS8, 0); -#endif - asm volatile("isync;msync;tlbwe;isync"); + write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
#ifdef CONFIG_ADDR_MAP if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index eda2959..d311ba2 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -480,6 +480,8 @@ extern int find_tlb_idx(void *addr, u8 tlbsel);
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
+extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); + #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \ .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot }