On 2024-12-15 10:18, J. Neuschäfer via B4 Relay wrote:
From: "J. Neuschäfer"j.ne@posteo.net
TBU and TBL are specified as two 32-bit registers that form a 64-bit value, but the calculation only shifted TBU by 16 bits.
Fix this by actually shifting 32 bits.
Signed-off-by: J. Neuschäferj.ne@posteo.net
drivers/timer/mpc83xx_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c index 9da74479aaa678bfab861950a770b216b604c433..f92009e4ccc8256d4c5f4d11e414dfc141f5a043 100644 --- a/drivers/timer/mpc83xx_timer.c +++ b/drivers/timer/mpc83xx_timer.c @@ -206,7 +206,7 @@ static u64 mpc83xx_timer_get_count(struct udevice *dev) tbl = mftb(); } while (tbu != mftbu());
- return (tbu * 0x10000ULL) + tbl;
return (uint64_t)tbu << 32 | tbl; }
static int mpc83xx_timer_probe(struct udevice *dev)
Reviewed-by: Sinan Akman sinan@writeme.com