Hi Andreas,
On 07/09/2013 05:01 PM, Andreas Naumann wrote:
It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx
When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear.
I read your link the other way round. If the #430973 errata fix is _not_ applied to r3p2 it gives a lot of segfaults. Unfortunately the thread has noc more information on that.
I dont know what bootloader the guy used, but he states that he needs to enable the errata fix in the kernel for the segfaults to disappear. I found exactly the same: Initially I had no errata fixes configured for the kernel, only when I added them the segfaults disappeared. However they also disappear if I remove the workarounds from kernel as well as u-boot, hence this patch.
Ok, understand.
<snip>
I join Albert's suggestion. Another solution could be to read the silicon revision and enable erratum workarounds on that information. It would be a step towards single binary.
So I'd rather do that, but can we map the ARM revision e.g. r2p1 to the TI die versions ES1.0, 1.1 and so on? Or can the ARM revision be read directly?
You should use the ARM revisions. They are available, but dunno how:
---8<--- ~ cat /proc/cpuinfo Processor : ARMv7 Processor rev 2 (v7l) BogoMIPS : 512.57 Features : swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x3 CPU part : 0xc08 CPU revision : 2 --->8---
AFAIK is CPU variant 'r3' and CPU revision 'p2' for this cpuinfo.
Regards
Andreas Bießmann