This patch is to separate the base trigger from the read/write transfer start addresses.
Base trigger register address (0x1c register) corresponds to the address which should be put on AHB bus to handle indirect transfer triggered before. To handle indirect transfer we need to issue addresses from (value of 0x1c) to (value of 0x1c) + 15*4 ("4" corresponds to size of SRAM location). There are no obstacles in issuing const address just equal to 0x1c. Important thing to note is that indirect trigger address has nothing in common with your physical or mapped NOR Flash address.
Transfer read/write start addresses (offset 0x68/0x78)should be programmed with the absolute flash address to be read/written.
plat->ahbbase has been renamed to plat->flashbase for clarity. plat->triggerbase is added in device tree for mapped spi flash address.
Signed-off-by: Vikas Manocha vikas.manocha@st.com --- arch/arm/dts/socfpga.dtsi | 1 + arch/arm/dts/stv0991.dts | 3 ++- drivers/spi/cadence_qspi.c | 13 +++++++------ drivers/spi/cadence_qspi.h | 5 +++-- drivers/spi/cadence_qspi_apb.c | 9 +++++---- 5 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 9b12420..c957f44 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -634,6 +634,7 @@ #size-cells = <0>; reg = <0xff705000 0x1000>, <0xffa00000 0x1000>; + <0x00000000 0x0010>; interrupts = <0 151 4>; clocks = <&qspi_clk>; ext-decoder = <0>; /* external decoder */ diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts index 556df82..f30a818 100644 --- a/arch/arm/dts/stv0991.dts +++ b/arch/arm/dts/stv0991.dts @@ -30,7 +30,8 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x80203000 0x100>, - <0x40000000 0x1000000>; + <0x40000000 0x1000000>, + <0x40000000 0x0000010>; clocks = <3750000>; ext-decoder = <0>; /* external decoder */ num-cs = <4>; diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..8b6de4f 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -150,7 +150,7 @@ static int cadence_spi_probe(struct udevice *bus) struct cadence_spi_priv *priv = dev_get_priv(bus);
priv->regbase = plat->regbase; - priv->ahbbase = plat->ahbbase; + priv->flashbase = plat->flashbase;
if (!priv->qspi_is_init) { cadence_qspi_apb_controller_init(plat); @@ -278,7 +278,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) const void *blob = gd->fdt_blob; int node = bus->of_offset; int subnode; - u32 data[4]; + u32 data[6]; int ret;
/* 2 base addresses are needed, lets get them from the DT */ @@ -289,7 +289,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) }
plat->regbase = (void *)data[0]; - plat->ahbbase = (void *)data[2]; + plat->flashbase = (void *)data[2]; + plat->trigger_base = (void *)data[4];
/* Use 500KHz as a suitable default */ plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", @@ -311,9 +312,9 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
- debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", - __func__, plat->regbase, plat->ahbbase, plat->max_hz, - plat->page_size); + debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d \ + page-size=%d\n", __func__, plat->regbase, plat->flashbase, \ + plat->trigger_base, plat->max_hz, plat->page_size);
return 0; } diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 98e57aa..7341339 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -17,7 +17,8 @@ struct cadence_spi_platdata { unsigned int max_hz; void *regbase; - void *ahbbase; + void *flashbase; + void *trigger_base;
u32 page_size; u32 block_size; @@ -30,7 +31,7 @@ struct cadence_spi_platdata {
struct cadence_spi_priv { void *regbase; - void *ahbbase; + void *flashbase; size_t cmd_len; u8 cmd_buf[32]; size_t data_len; diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 7174f7c..e6ff0e0 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -467,7 +467,8 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
/* Indirect mode configurations */ writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); - writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); + writel((u32)plat->trigger_base, + plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Disable all interrupts */ writel(0, plat->regbase + CQSPI_REG_IRQMASK); @@ -637,7 +638,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
/* Get address */ addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); - writel((u32)plat->ahbbase + addr_value, \ + writel((u32)plat->flashbase + addr_value, \ plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
/* The remaining lenght is dummy bytes. */ @@ -686,7 +687,7 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, udelay(1);
if (cadence_qspi_apb_read_fifo_data((void*)rxbuf, - (const void *) plat->ahbbase, rxlen)) + (const void *) plat->trigger_base, rxlen)) goto failrd;
/* Check flash indirect controller */ @@ -729,7 +730,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
/* Setup write address. */ reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); - writel((u32)plat->ahbbase + reg, \ + writel((u32)plat->flashbase + reg, \ plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
reg = readl(plat->regbase + CQSPI_REG_SIZE);