[PATCH 0/2] Add SiFive private L2 cache driver

SiFive private L2 cache is per core cache, add this driver to control its features by a MMIO register. In this series, we try to enable the power gating feature of pL2 cache in SPL stage

Zong Li (2): cache: add sifive private L2 cache driver riscv: cache: support cache enable in SPL stage

arch/riscv/lib/sifive_cache.c | 21 +++++++++++++++ drivers/cache/Kconfig | 7 +++++ drivers/cache/Makefile | 1 + drivers/cache/cache-sifive-pl2.c | 44 ++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 drivers/cache/cache-sifive-pl2.c