25 Mar
2020
25 Mar
'20
9:35 p.m.
On 3/25/20 2:27 PM, Jan Kiszka wrote:
From: Jan Kiszka jan.kiszka@siemens.com
We need to align the cache buffer to ARCH_DMA_MINALIGN in order to avoid access errors like
CACHE: Misaligned operation at range [be0231e0, be0235e0]
seen on the MCIMX7SABRE.
Fixes: d5aee659f217 ("fs: ext4: cache extent data") Signed-off-by: Jan Kiszka jan.kiszka@siemens.com
Reviewed-by: Stephen Warren swarren@nvidia.com
It's probably just a fluke that this happens to show up on some SoCs/boards/configurations but not others. Or perhaps the MINALIGN value differs?