855873: An eviction might overtake a cache clean operation Workaround: The erratum can be avoided by upgrading cache clean by address operations to cache clean and invalidate operations. For Cortex-A53 r0p3 and later release, this can be achieved by setting CPUACTLR.ENDCCASCI to 1.
This patch is to implement the workaround for this erratum.
Signed-off-by: Alison Wang alison.wang@nxp.com --- Changes in v2: - Check the revision of Cortex-A53 and apply the erratum to r0p3 and later release. - Fix the mistake in the commit description.
arch/arm/Kconfig | 3 +++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 ++ arch/arm/cpu/armv8/start.S | 20 +++++++++++++++++++- 3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d43aaac..4a885a3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -103,6 +103,9 @@ config ARM_ERRATA_852421 config ARM_ERRATA_852423 bool
+config ARM_ERRATA_855873 + bool + config CPU_ARM720T bool select SYS_CACHE_SHIFT_5 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5825f9b..63658b5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,6 +1,7 @@ config ARCH_LS1012A bool select ARMV8_SET_SMPEN + select ARM_ERRATA_855873 select FSL_LSCH2 select SYS_FSL_DDR_BE select SYS_FSL_MMDC @@ -11,6 +12,7 @@ config ARCH_LS1012A config ARCH_LS1043A bool select ARMV8_SET_SMPEN + select ARM_ERRATA_855873 select FSL_LSCH2 select SYS_FSL_DDR select SYS_FSL_DDR_BE diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 5c500be..6ca054b 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -170,7 +170,10 @@ reset_sctrl: WEAK(apply_core_errata)
mov x29, lr /* Save LR */ - /* For now, we support Cortex-A57 specific errata only */ + /* For now, we support Cortex-A53, Cortex-A57 specific errata */ + + /* Check if we are running on a Cortex-A53 core */ + branch_if_a53_core x0, apply_a53_core_errata
/* Check if we are running on a Cortex-A57 core */ branch_if_a57_core x0, apply_a57_core_errata @@ -178,6 +181,21 @@ WEAK(apply_core_errata) mov lr, x29 /* Restore LR */ ret
+apply_a53_core_errata: + +#ifdef CONFIG_ARM_ERRATA_855873 + mrs x0, midr_el1 + and x0, x0, #0xf + cmp x0, #3 + b.lt 0b + + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Enable data cache clean as data cache clean/invalidate */ + orr x0, x0, #1 << 44 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + b 0b + apply_a57_core_errata:
#ifdef CONFIG_ARM_ERRATA_828024