The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com --- board/sbc8548/sbc8548.c | 8 +++++++- board/sbc8548/tlb.c | 22 +++++++++++++++------- include/configs/sbc8548.h | 42 ++++++++++++++++++++++++++++++++++++++---- 3 files changed, 60 insertions(+), 12 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index ce998e1..f4bfd92 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -149,7 +149,7 @@ local_bus_init(void) void sdram_init(void) { -#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) +#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx; volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); @@ -169,6 +169,12 @@ sdram_init(void) out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM); asm("msync");
+ out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM); + asm("msync"); + + out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM); + asm("msync"); + out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); asm("msync");
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index dbb9ba8..e173245 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -88,14 +88,22 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* * TLB 5: 64M Cacheable, non-guarded - * 0xf0000000 64M LBC SDRAM + * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_64M, 1),
/* - * TLB 6: 16M Cacheable, non-guarded + * TLB 6: 64M Cacheable, non-guarded + * 0xf4000000 64M LBC SDRAM Second half + */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision @@ -103,23 +111,23 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_16M, 1), + 0, 7, BOOKE_PAGESZ_16M, 1),
/* - * TLB 7: 4M Non-cacheable, guarded + * TLB 8: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_4M, 1), + 0, 8, BOOKE_PAGESZ_4M, 1),
/* - * TLB 8: 4M Non-cacheable, guarded + * TLB 9: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4M, 1), + 0, 9, BOOKE_PAGESZ_4M, 1),
};
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 8edba20..4751013 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -196,13 +196,13 @@ #define CONFIG_SYS_EEPROM_BASE 0xf8b00000
/* - * SDRAM on the Local Bus + * SDRAM on the Local Bus (CS3 and CS4) */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
/* - * Base Register 3 and Option Register 3 configure SDRAM. + * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. * * For BR3, need: @@ -220,7 +220,7 @@ #define CONFIG_SYS_BR3_PRELIM 0xf0001861
/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * * For OR3, need: * 64MB mask for AM, OR3[0:7] = 1111 1100 @@ -235,6 +235,40 @@
#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
+/* + * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. + * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. + * + * For BR4, need: + * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 + * + */ + +#define CONFIG_SYS_BR4_PRELIM 0xf4001861 + +/* + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR4, need: + * 64MB mask for AM, OR3[0:7] = 1111 1100 + * XAM, OR3[17:18] = 11 + * 10 columns OR3[19-21] = 011 + * 12 rows OR3[23-25] = 011 + * EAD set for extra time OR[31] = 0 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 + */ + +#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 + #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */