Hi,
On 27/06/18 11:49, Icenowy Zheng wrote:
在 2018-06-27三的 10:46 +0100，Andre Przywara写道：
Hi,
On 25/06/18 11:37, Icenowy Zheng wrote:
The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo. Both the controller and the PHY seem to be originate from DesignWare, and are similar to the ones in ZynqMP SoCs.
This commit introduces an initial DRAM driver for H6, which contains only LPDDR3 support. The currently known SBCs with H6 all come with LPDDR3 memory, including Pine H64 and several Orange Pi's.
The BSP DRAM initialization code is closed source and violates GPL. Code in this commit is written by experimenting, referring the code/document of other users of the IPs (mainly the ZynqMP, as it's the only found PHY reference) and disassebling the BSP blob.
Thanks for Jernej Skrabec for review and fix some issues in this driver (including the most critical one which made it to work), and rewrite some code from register dump!
It seems that you guys really spent a lot of time and work into this, thanks a lot for that! Just skimming over the code, that looks vaguely similar to the existing dram_sunxi_dw.c driver. I guess you considered and dismissed that
They're quite different. The "sunxi_dw" memory controller is a controller+PHY combo, and address translation happen on the "mctl_com" part, with just address feed; the H6 memory controller have dedicated controller and PHY parts, like A23/A80, with a similar but enhanced controller and a quite different PHY (both the controller and the PHY are similar to the ones on ZynqMP), and address translation is also dropped from mctl_com, instead done by the memory controller (the ADDRMAPx registers).
The main part that should seem similar on all SoCs is the mctl_com priority code, which is not only similar with sunxi_dw but also with A23/A33/A83T/A80 (although I think A33/A83T are also similar with sunxi_dw).
Other similar parts are similar because they all originate from Allwinner's code, but with different controller (different offsets, different bit definition, etc).
Thanks a lot for that comprehensive answer, and I was afraid of something like that :-)
Maybe I should add a comment somewhere to describe the different?
Yeah, it would be helpful to not loose this information. I was always wondering if we should try to unify DRAM controller drivers, starting with the other Allwinner SoCs, but also looking at other platforms. I see that this is quite some work, but this research of yours above would be quite beneficial for that task.
Cheers, Andre.