Enable DDR PHY mode support for Micron,ISSI,GIGA and Macronix Flash.
We are dividing the below series into three sets. This represents the initial set, wherein we have activated DDR mode support for flashes. https://lore.kernel.org/all/cover.1701853668.git.tejas.arvind.bhumkar@amd.co...
The series is based on: https://lore.kernel.org/all/20240304031046.25998-1-venkatesh.abbarapu@amd.co...
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Ashok Reddy Soma (7): spi: cadence_qspi: Write aligned byte length to ahbbase spi: cadence_qspi: Clean up registers in init spi: cadence_qspi: Initialize read and write watermark registers mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes mtd: spi-nor: Check SNOR_F_IO_MODE_EN_VOLATILE only if SFDP is enabled mtd: spi-nor: Add support for cross die read in dual flash configuration mtd: spi-nor: Enable DTR octal flash program
T Karthik Reddy (5): spi: cadence_qspi: Add support for DDR PHY mode spi: cadence-qspi: reset the ospi controller spi: cadence_ospi_versal: ospi ddr changes in cadence ospi versal driver spi: cadence_qspi: Add spi mem dtr support ops spi: mtd: Use split reads if multi-die flag is set
Tejas Bhumkar (6): arm64: versal: Enable defconfig for Micron octal flashes mtd: spi-nor: Update erase operation function arm64: versal: Enable soft reset support for xspi flashes mtd: spi-nor: Enable DDR mode functionality with ISSI flash mtd: spi-nor: Enable DDR mode functionality with Gigadevice flash mtd: spi-nor: Enable DDR mode functionality with Macronix flash
Venkatesh Yadav Abbarapu (1): mtd: spi-nor: Update block protection flags for flash parts
configs/xilinx_versal_virt_defconfig | 3 + drivers/mtd/spi/sf_internal.h | 2 + drivers/mtd/spi/spi-nor-core.c | 185 ++++++++++--- drivers/mtd/spi/spi-nor-ids.c | 36 +-- drivers/spi/cadence_ospi_versal.c | 76 +++++- drivers/spi/cadence_qspi.c | 378 ++++++++++++++++++++++++++- drivers/spi/cadence_qspi.h | 57 ++++ drivers/spi/cadence_qspi_apb.c | 73 +++++- include/spi.h | 7 +- 9 files changed, 740 insertions(+), 77 deletions(-)