Signed-off-by: Vipin vipin.kumar@st.com --- board/spear/common/spr_lowlevel_init.S | 202 ++++++++++++++++++ board/spear/common/spr_misc.c | 270 ++++++++++++++++++++++++ board/spear/spear600/Makefile | 52 +++++ board/spear/spear600/config.mk | 39 ++++ board/spear/spear600/spr600_board.c | 53 +++++ common/cmd_bdinfo.c | 20 ++ cpu/arm926ejs/spear/Makefile | 52 +++++ cpu/arm926ejs/spear/reset.c | 49 +++++ cpu/arm926ejs/spear/timer.c | 148 +++++++++++++ include/asm-arm/arch-spear/spr_defs.h | 31 +++ include/asm-arm/arch-spear/spr_emi.h | 55 +++++ include/asm-arm/arch-spear/spr_gpt.h | 83 ++++++++ include/asm-arm/arch-spear/spr_syscntl.h | 38 ++++ include/asm-arm/arch-spear/spr_xloader_table.h | 67 ++++++ include/asm-arm/u-boot.h | 5 + include/configs/spear600.h | 260 +++++++++++++++++++++++ 16 files changed, 1424 insertions(+), 0 deletions(-) create mode 100755 board/spear/common/spr_lowlevel_init.S create mode 100755 board/spear/common/spr_misc.c create mode 100755 board/spear/spear600/Makefile create mode 100755 board/spear/spear600/config.mk create mode 100755 board/spear/spear600/spr600_board.c create mode 100755 cpu/arm926ejs/spear/Makefile create mode 100755 cpu/arm926ejs/spear/reset.c create mode 100755 cpu/arm926ejs/spear/timer.c create mode 100644 include/asm-arm/arch-spear/spr_defs.h create mode 100755 include/asm-arm/arch-spear/spr_emi.h create mode 100755 include/asm-arm/arch-spear/spr_gpt.h create mode 100644 include/asm-arm/arch-spear/spr_syscntl.h create mode 100755 include/asm-arm/arch-spear/spr_xloader_table.h create mode 100755 include/configs/spear600.h
diff --git a/board/spear/common/spr_lowlevel_init.S b/board/spear/common/spr_lowlevel_init.S new file mode 100755 index 0000000..dcacff8 --- /dev/null +++ b/board/spear/common/spr_lowlevel_init.S @@ -0,0 +1,202 @@ +/* + * (C) Copyright 2006 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + +/* + * platform specific initializations are already done in Xloader + * Initializations already done include + * DDR, PLLs, IP's clock enable and reset release etc + */ +.globl lowlevel_init +lowlevel_init: + /* By default, U-Boot switches CPU to low-vector */ + /* Revert this as we work in high vector even in U-Boot */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x00002000 + mcr p15, 0, r0, c1, c0, 0 + mov pc, lr + +#if defined (CONFIG_CMD_SETFREQ) + +/* ;void setfreq(unsigned int device, unsigned int frequency) */ +.global setfreq +setfreq: + stmfd sp!,{r14} + stmfd sp!,{r0-r12} + + mov r8,sp + ldr sp,SRAM_STACK_V + + /* ;Saving the function arguements for later use */ + mov r4,r0 + mov r5,r1 + + /* ;Putting DDR into self refresh */ + ldr r0,DDR_07_V + ldr r1,[r0] + ldr r2,DDR_ACTIVE_V + bic r1, r1, r2 + str r1,[r0] + ldr r0,DDR_57_V + ldr r1,[r0] + ldr r2,CYCLES_MASK_V + bic r1, r1, r2 + ldr r2,REFRESH_CYCLES_V + orr r1, r1, r2, lsl #16 + str r1,[r0] + ldr r0,DDR_07_V + ldr r1,[r0] + ldr r2,SREFRESH_MASK_V + orr r1, r1, r2 + str r1,[r0] + + b 1f + .align 5 +1: + /* ;Delay to ensure self refresh mode */ + ldr r0,SREFRESH_DELAY_V +1: + sub r0,r0,#1 + cmp r0,#0 + bne 1b + + /* ;Putting system in slow mode */ + ldr r0,SCCTRL_V + mov r1,#2 + str r1,[r0] + + /* ;Changing PLL(1/2) frequency */ + mov r0,r4 + mov r1,r5 + + cmp r4,#0 + beq 1f + + /* ;Change PLL2 (DDR frequency) */ + ldr r6,PLL2_FREQ_V + ldr r7,PLL2_CNTL_V + b 2f + +1: + /* ;Change PLL1 (CPU frequency) */ + ldr r6,PLL1_FREQ_V + ldr r7,PLL1_CNTL_V + +2: + mov r0,r6 + ldr r1,[r0] + ldr r2,PLLFREQ_MASK_V + bic r1,r1,r2 + mov r2,r5,lsr#1 + orr r1,r1,r2,lsl#24 + str r1,[r0] + + mov r0,r7 + ldr r1,P1C0A_V + str r1,[r0] + /* ;ldr r0,r7 */ + ldr r1,P1C0E_V + str r1,[r0] + /* ;ldr r0,r7 */ + ldr r1,P1C06_V + str r1,[r0] + /* ;ldr r0,r7 */ + ldr r1,P1C0E_V + str r1,[r0] + +1: + ldr r1,[r0] + and r1,r1,#1 + cmp r1,#0 + beq 1b + + /* ;Putting system back to normal mode */ + ldr r0,SCCTRL_V + mov r1,#4 + str r1,[r0] + + /* ;Putting DDR back to normal */ + ldr r0,DDR_07_V + ldr r1,[R0] + ldr r2,SREFRESH_MASK_V + bic r1, r1, r2 + str r1,[r0] + ldr r2,DDR_ACTIVE_V + orr r1, r1, r2 + str r1,[r0] + + /* ;Delay to ensure self refresh mode */ + ldr r0,SREFRESH_DELAY_V +1: + sub r0,r0,#1 + cmp r0,#0 + bne 1b + + mov sp,r8 + /* ;Resuming back to code */ + ldmia sp!,{r0-r12} + ldmia sp!,{pc} + +SCCTRL_V: + .word 0xfca00000 +PLL1_FREQ_V: + .word 0xfca8000C +PLL1_CNTL_V: + .word 0xfca80008 +PLL2_FREQ_V: + .word 0xfca80018 +PLL2_CNTL_V: + .word 0xfca80014 +PLLFREQ_MASK_V: + .word 0xff000000 +P1C0A_V: + .word 0x1C0A +P1C0E_V: + .word 0x1C0E +P1C06_V: + .word 0x1C06 + +SREFRESH_DELAY_V: + .word 0x9999 +SRAM_STACK_V: + .word 0xD2800600 +DDR_07_V: + .word 0xfc60001c +DDR_ACTIVE_V: + .word 0x01000000 +DDR_57_V: + .word 0xfc6000e4 +CYCLES_MASK_V: + .word 0xffff0000 +REFRESH_CYCLES_V: + .word 0xf0f0 +SREFRESH_MASK_V: + .word 0x00010000 + +.global setfreq_sz +setfreq_sz: + .word setfreq_sz - setfreq + +#endif + diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c new file mode 100755 index 0000000..83698eb --- /dev/null +++ b/board/spear/common/spr_misc.c @@ -0,0 +1,270 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <net.h> +#include <asm/io.h> +#include <asm/arch/spr_emi.h> +#include <asm/arch/spr_xloader_table.h> +#include <asm/arch/spr_defs.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + struct xloader_table *xloader_tb = + (struct xloader_table *) XLOADER_TABLE_ADDRESS; + struct xloader_table_1_1 *table_1_1; + struct xloader_table_1_2 *table_1_2; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1, + PHYS_SDRAM_1_MAXSIZE); + + if (XLOADER_TABLE_VERSION_1_1 == xloader_tb->table_version) { + table_1_1 = &xloader_tb->table.table_1_1; + gd->bd->dramfreq = table_1_1->ddrfreq; + gd->bd->dramtype = table_1_1->ddrtype; + + } else if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) { + table_1_2 = &xloader_tb->table.table_1_2; + gd->bd->dramfreq = table_1_2->ddrfreq; + gd->bd->dramtype = table_1_2->ddrtype; + } else { + gd->bd->dramfreq = -1; + } + + return 0; +} + +int misc_init_r(void) +{ +#if defined(CONFIG_CMD_NET) + uchar mac_id[6]; + + if (!i2c_read_mac(mac_id)) + eth_setenv_enetaddr("ethaddr", mac_id); +#endif + setenv("verify", "n"); + +#if defined(CONFIG_SPEAR_USBTTY) + setenv("stdin", "usbtty"); + setenv("stdout", "usbtty"); + setenv("stderr", "usbtty"); +#endif + return 0; +} + +#ifdef CONFIG_SPEAR_EMI +struct cust_emi_para { + unsigned int tap; + unsigned int tsdp; + unsigned int tdpw; + unsigned int tdpr; + unsigned int tdcs; + unsigned int control; +}; + +/* EMI timing setting of m28w640hc of linux kernel */ +const struct cust_emi_para emi_timing_m28w640hc = { + .tap = 0x10, + .tsdp = 0x05, + .tdpw = 0x0a, + .tdpr = 0x0a, + .tdcs = 0x05, +}; + +/* EMI timing setting of bootrom */ +const struct cust_emi_para emi_timing_bootrom = { + .tap = 0xf, + .tsdp = 0x0, + .tdpw = 0xff, + .tdpr = 0x111, + .tdcs = 0x02, +}; + +void spear_emi_init(void) +{ + const struct cust_emi_para *p = &emi_timing_m28w640hc; + struct emi_regs *emi_regs_p = + (struct emi_regs *)CONFIG_SPEAR_EMIBASE; + unsigned int cs; + unsigned int val, tmp; + + val = readl(CONFIG_SPEAR_RASBASE); + + if (val & EMI_ACKMSK) + tmp = 0x3f; + else + tmp = 0x0; + + writel(tmp, &emi_regs_p->ack); + + for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) { + writel(p->tap, &emi_regs_p->bank_regs[cs].tap); + writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp); + writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw); + writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr); + writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs); + writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3), + &emi_regs_p->bank_regs[cs].control); + } +} +#endif + +int spear_board_init(ulong mach_type) +{ + struct xloader_table *xloader_tb = + (struct xloader_table *) XLOADER_TABLE_ADDRESS; + struct xloader_table_1_2 *table_1_2; + + gd->bd->bi_arch_number = mach_type; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR; + + if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) { + table_1_2 = &xloader_tb->table.table_1_2; + memcpy(gd->bd->version, table_1_2->version, + sizeof(gd->bd->version)); + } +#ifdef CONFIG_SPEAR_EMI + spear_emi_init(); +#endif + return 0; +} + +#if defined(CONFIG_CMD_SETFREQ) + +#define CPU 0 +#define DDR 1 + +int do_setfreq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + void (*sram_setfreq) (unsigned int, unsigned int); + unsigned int frequency; + + if (argc != 3) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + frequency = simple_strtoul(argv[2], NULL, 0); + + if (frequency > 333) { + printf("Frequency is limited to 333MHz\n"); + return 1; + } + sram_setfreq = memcpy((void *)0xD2801000, setfreq, setfreq_sz); + + if (!strcmp(argv[1], "ddr")) { + sram_setfreq(DDR, frequency); + printf("DDR frequency changed to %u\n", frequency); + + } else if (!strcmp(argv[1], "cpu")) { + sram_setfreq(CPU, frequency); + printf("CPU frequency changed to %u\n", frequency); + } else { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + return 0; +} + +U_BOOT_CMD(setfreq, 3, 1, do_setfreq, + "change ddr/cpu frequency", "device[ddr/cpu] frequency"); +#endif + +#if defined(CONFIG_CMD_NET) +static int i2c_read_mac(u8 *buffer) +{ + unsigned char buf[2]; + + i2c_read(0x50, 0x0, 1, buf, 2); + + /* check if valid MAC address is saved in I2C EEPROM or not? */ + if ((buf[0] == 0x55) && (buf[1] == 0xAA)) { + /* Valid MAC address is saved in I2C EEPROM, + read the MAC address from the + EEPROM & update the buffer */ + i2c_read(0x50, 0x2, 1, buffer, 6); + return 0; + } else { + return -1; + } +} + +int do_writemac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned char buf[2]; + unsigned char mac[6]; + unsigned int reg; + char *s, *e; + + if (argc != 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + s = argv[1]; + for (reg = 0; reg < 6; ++reg) { + mac[reg] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + buf[0] = 0x55; + buf[1] = 0xAA; + i2c_write(0x50, /* Chip address */ + 0x0, /* Offset */ + 1, /* Address length */ + buf, /* buffer */ + 2); /* Length */ + + buf[0] = 0x44; + buf[1] = 0x66; + + i2c_read(0x50, /* Chip address */ + 0x0, /* Offset */ + 1, /* Address length */ + buf, /* buffer */ + 2); /* Length */ + + /* check if valid MAC address is saved in I2C EEPROM or not? */ + if ((buf[0] == 0x55) && (buf[1] == 0xAA)) { + i2c_write(0x50, 0x2, 1, mac, 6); + puts("I2C EEPROM written with mac address \n"); + return 0; + } else { + puts("I2C EEPROM writing failed \n"); + return -1; + } +} + +U_BOOT_CMD(writemac, 2, 1, do_writemac, + "write mac address in I2C memory", "XX:XX:XX:XX:XX:XX"); +#endif + diff --git a/board/spear/spear600/Makefile b/board/spear/spear600/Makefile new file mode 100755 index 0000000..cce4c89 --- /dev/null +++ b/board/spear/spear600/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := spr600_board.o \ + ../common/spr_misc.o +SOBJS := ../common/spr_lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/spear600/config.mk b/board/spear/spear600/config.mk new file mode 100755 index 0000000..90a6cf9 --- /dev/null +++ b/board/spear/spear600/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2009 +# Vipin Kumar, ST Microelectronics vipin.kumar@st.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +TEXT_BASE = 0x00700000 + +ALL += $(obj)u-boot.img + +# Environment variables in NAND +ifeq ($(ENV),NAND) +PLATFORM_RELFLAGS += -DENV_IN_NAND +endif + +# Compile uboot as USB boot firmware +ifeq ($(CONSOLE),USB) +PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY +endif + diff --git a/board/spear/spear600/spr600_board.c b/board/spear/spear600/spr600_board.c new file mode 100755 index 0000000..378b3b9 --- /dev/null +++ b/board/spear/spear600/spr600_board.c @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <nand.h> +#include <asm/io.h> +#include <asm/arch/spr_defs.h> +#include <asm/arch/spr_misc.h> +#include <asm/arch/spr_nand.h> + +int board_init(void) +{ + return spear_board_init(MACH_TYPE_SPEAR600); +} + +/** + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +int board_nand_init(struct nand_chip *nand) +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) { + return spear_nand_init(nand); + } else { + return -1; + } +} diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 11c1547..412cad6 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -27,6 +27,10 @@ #include <common.h> #include <command.h>
+#if defined(CONFIG_SPEAR600) || defined(CONFIG_SPEAR3XX) +#include <asm/arch/spr_xloader_table.h> +#endif + DECLARE_GLOBAL_DATA_PTR;
static void print_num(const char *, ulong); @@ -339,6 +343,22 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif printf ("baudrate = %d bps\n", bd->bi_baudrate);
+#if defined(CONFIG_SPEAR600) || defined(CONFIG_SPEAR3XX) + if (bd->dramfreq == -1) + printf("DDR Freq = Not Known\n"); + else + printf("DDR Freq = %d\n", bd->dramfreq); + + if (bd->dramtype == DDRMOBILE) + printf("DDR Type = MOBILE\n"); + else if (bd->dramtype == DDR2) + printf("DDR Type = DDR2\n"); + else + printf("DDR Type = Not Known\n"); + + printf("Xloader Rev = %s\n", bd->version); +#endif + return 0; }
diff --git a/cpu/arm926ejs/spear/Makefile b/cpu/arm926ejs/spear/Makefile new file mode 100755 index 0000000..bf8dfa8 --- /dev/null +++ b/cpu/arm926ejs/spear/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS := reset.o \ + timer.o +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/spear/reset.c b/cpu/arm926ejs/spear/reset.c new file mode 100755 index 0000000..1bce95f --- /dev/null +++ b/cpu/arm926ejs/spear/reset.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/spr_syscntl.h> + +void reset_cpu(ulong ignored) +{ + struct syscntl_regs *syscntl_regs_p = + (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE; + + printf("System is going to reboot ...\n"); + + /* This 1 second delay will allow the above message + to be printed before reset */ + udelay((1000 * 1000)); + + /* Going into slow mode before resetting SOC */ + writel(0x02, &syscntl_regs_p->scctrl); + + /* Writing any value to the system status register will + reset the SOC */ + writel(0x00, &syscntl_regs_p->scsysstat); + + /* system will restart */ + while (1) + ; +} diff --git a/cpu/arm926ejs/spear/timer.c b/cpu/arm926ejs/spear/timer.c new file mode 100755 index 0000000..8bcc37f --- /dev/null +++ b/cpu/arm926ejs/spear/timer.c @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/spr_gpt.h> +#include <asm/arch/spr_misc.h> + +static struct gpt_regs *const gpt_regs_p = + (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE; + +static struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + +#define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING) + +static ulong timestamp; +static ulong lastdec; + +int timer_init(void) +{ + u32 synth; + + /* Prescaler setting */ +#if defined(CONFIG_SPEAR3XX) + writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg); + synth = MISC_GPT4SYNTH; +#elif defined(CONFIG_SPEAR600) + writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg); + synth = MISC_GPT3SYNTH; +#endif + + writel(readl(&misc_regs_p->periph_clk_cfg) | synth, + &misc_regs_p->periph_clk_cfg); + + /* disable timers */ + writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control); + + /* load value for free running */ + writel(GPT_FREE_RUNNING, &gpt_regs_p->compare); + + /* auto reload, start timer */ + writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control); + + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void __udelay(unsigned long usec) +{ + ulong tmo; + ulong start = get_timer_masked(); + ulong rndoff; + + rndoff = (usec % 500) ? 1 : 0; + + /* 13 timer ticks gives 500 microsecconds delay */ + tmo = ((usec/500) + rndoff) * 13; + + while ((ulong) (get_timer_masked() - start) < tmo) + ; +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER(); + + if (now >= lastdec) { + /* normal mode */ + timestamp += now - lastdec; + } else { + /* we have an overflow ... */ + timestamp += now + GPT_FREE_RUNNING - lastdec; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked(unsigned long usec) +{ + return udelay(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/include/asm-arm/arch-spear/spr_defs.h b/include/asm-arm/arch-spear/spr_defs.h new file mode 100644 index 0000000..76aa928 --- /dev/null +++ b/include/asm-arm/arch-spear/spr_defs.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPR_DEFS_H__ +#define __SPR_DEFS_H__ + +extern int spear_board_init(ulong); +extern void setfreq(unsigned int, unsigned int); +extern unsigned int setfreq_sz; + +#endif diff --git a/include/asm-arm/arch-spear/spr_emi.h b/include/asm-arm/arch-spear/spr_emi.h new file mode 100755 index 0000000..cfeb0b1 --- /dev/null +++ b/include/asm-arm/arch-spear/spr_emi.h @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2009 + * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPEAR_EMI_H__ +#define __SPEAR_EMI_H__ + +#ifdef CONFIG_SPEAR_EMI + +struct emi_bank_regs { + u32 tap; + u32 tsdp; + u32 tdpw; + u32 tdpr; + u32 tdcs; + u32 control; +}; + +struct emi_regs { + struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS]; + u32 tout; + u32 ack; + u32 irq; +}; + +#define EMI_ACKMSK 0x40 + +/* control register definitions */ +#define EMI_CNTL_ENBBYTEW (1 << 2) +#define EMI_CNTL_ENBBYTER (1 << 3) +#define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW) + +#endif + +#endif + diff --git a/include/asm-arm/arch-spear/spr_gpt.h b/include/asm-arm/arch-spear/spr_gpt.h new file mode 100755 index 0000000..2b870e9 --- /dev/null +++ b/include/asm-arm/arch-spear/spr_gpt.h @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPR_GPT_H +#define _SPR_GPT_H + +struct gpt_regs { + u8 reserved[0x80]; + u32 control; + u32 status; + u32 compare; + u32 count; + u32 capture_re; + u32 capture_fe; +}; + +/* + * TIMER_CONTROL register settings + */ + +#define GPT_PRESCALER_MASK 0x000F +#define GPT_PRESCALER_1 0x0000 +#define GPT_PRESCALER_2 0x0001 +#define GPT_PRESCALER_4 0x0002 +#define GPT_PRESCALER_8 0x0003 +#define GPT_PRESCALER_16 0x0004 +#define GPT_PRESCALER_32 0x0005 +#define GPT_PRESCALER_64 0x0006 +#define GPT_PRESCALER_128 0x0007 +#define GPT_PRESCALER_256 0x0008 + +#define GPT_MODE_SINGLE_SHOT 0x0010 +#define GPT_MODE_AUTO_RELOAD 0x0000 + +#define GPT_ENABLE 0x0020 + +#define GPT_CAPT_MODE_MASK 0x00C0 +#define GPT_CAPT_MODE_NONE 0x0000 +#define GPT_CAPT_MODE_RE 0x0040 +#define GPT_CAPT_MODE_FE 0x0080 +#define GPT_CAPT_MODE_BOTH 0x00C0 + +#define GPT_INT_MATCH 0x0100 + +#define GPT_INT_FE 0x0200 + +#define GPT_INT_RE 0x0400 + +/* + * TIMER_STATUS register settings + */ + +#define GPT_STS_MATCH 0x0001 +#define GPT_STS_FE 0x0002 +#define GPT_STS_RE 0x0004 + +/* + * TIMER_COMPARE register settings + */ + +#define GPT_FREE_RUNNING 0xFFFF + +#endif diff --git a/include/asm-arm/arch-spear/spr_syscntl.h b/include/asm-arm/arch-spear/spr_syscntl.h new file mode 100644 index 0000000..3c92f09 --- /dev/null +++ b/include/asm-arm/arch-spear/spr_syscntl.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2009 + * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +struct syscntl_regs { + u32 scctrl; + u32 scsysstat; + u32 scimctrl; + u32 scimsysstat; + u32 scxtalctrl; + u32 scpllctrl; + u32 scpllfctrl; + u32 scperctrl0; + u32 scperctrl1; + u32 scperen; + u32 scperdis; + const u32 scperclken; + const u32 scperstat; +}; diff --git a/include/asm-arm/arch-spear/spr_xloader_table.h b/include/asm-arm/arch-spear/spr_xloader_table.h new file mode 100755 index 0000000..d75dae2 --- /dev/null +++ b/include/asm-arm/arch-spear/spr_xloader_table.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPR_XLOADER_TABLE_H +#define _SPR_XLOADER_TABLE_H + +#define XLOADER_TABLE_VERSION_1_1 2 +#define XLOADER_TABLE_VERSION_1_2 3 + +#define XLOADER_TABLE_ADDRESS 0xD2801FF0 + +#define DDRMOBILE 1 +#define DDR2 2 + +#define REV_BA 1 +#define REV_AA 2 +#define REV_AB 3 + +struct xloader_table_1_1 { + unsigned short ddrfreq; + unsigned char ddrsize; + unsigned char ddrtype; + + unsigned char soc_rev; +} __attribute__ ((packed)); + +struct xloader_table_1_2 { + unsigned const char *version; + + unsigned short ddrfreq; + unsigned char ddrsize; + unsigned char ddrtype; + + unsigned char soc_rev; +} __attribute__ ((packed)); + +union table_contents { + struct xloader_table_1_1 table_1_1; + struct xloader_table_1_2 table_1_2; +}; + +struct xloader_table { + unsigned char table_version; + union table_contents table; +} __attribute__ ((packed)); + +#endif diff --git a/include/asm-arm/u-boot.h b/include/asm-arm/u-boot.h index cfd5a9b..0ead5d9 100644 --- a/include/asm-arm/u-boot.h +++ b/include/asm-arm/u-boot.h @@ -47,6 +47,11 @@ typedef struct bd_info { ulong start; ulong size; } bi_dram[CONFIG_NR_DRAM_BANKS]; +#if defined(CONFIG_SPEAR600) || defined(CONFIG_SPEAR3XX) + unsigned char version[32]; + int dramfreq; + int dramtype; +#endif } bd_t;
#define bi_env_data bi_env->data diff --git a/include/configs/spear600.h b/include/configs/spear600.h new file mode 100755 index 0000000..755114d --- /dev/null +++ b/include/configs/spear600.h @@ -0,0 +1,260 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SPEAR600 1 + +/* + * Ethernet MAC driver configuration + */ +/* #define CONFIG_SPEARMAC */ +/* #define CONFIG_ETHAUTONEG */ +/* #define CONFIG_ETHDEBUG */ + +/* + * USBD driver configuration + */ +#define CONFIG_SPEARUDC +#define CONFIG_USB_DEVICE +#define CONFIG_USB_TTY +#define CONFIG_SYS_USBD_BASE (0xE1100000) +#define CONFIG_SYS_PLUG_BASE (0xE1200000) +#define CONFIG_SYS_FIFO_BASE (0xE1000800) +#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" +#define CONFIG_USBD_MANUFACTURER "ST Microelectronics" + +#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm" + +/* + * I2C driver configuration + */ +#define CONFIG_HARD_I2C +#define CONFIG_SPEARI2C +#define CONFIG_SYS_I2C_BASE 0xD0200000 +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x02 + +/* #define CONFIG_SYS_I2C_MULTI_EEPROMS */ +/* #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 0x1 */ + +/* + * SMI driver configuration + */ +#define CONFIG_SPEARSMI +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_SMI_BASE 0xFC000000 + +/* + * Serial Configuration (PL011) + */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) +#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1 } +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ + 57600, 115200 } +#define CONFIG_SYS_SERIAL0 0xD0000000 +#define CONFIG_SYS_SERIAL1 0xD0080000 + +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* + * Platform specific defines (SPEAr) + */ +#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000) +#define CONFIG_SPEAR_TIMERBASE (0xFC800000) +#define CONFIG_SPEAR_MISCBASE (0xFCA80000) +#define CONFIG_SYS_HZ (26000) + +/* + * Board Specific Defines (SPEAr600) + */ + +/* + * FLASH Configuration + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BASE (0xF8000000) +#define CONFIG_SYS_FLASH_BANK_SIZE (0x01000000) +#define CONFIG_SYS_FLASH_ADDR_BASE {0xF8000000, 0xF9000000} +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) + +/* + * NAND FLASH Configuration + */ +#define CONFIG_NAND_SPEAR 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0xD2000000 +#define CONFIG_SYS_NAND_CLE (1 << 16) +#define CONFIG_SYS_NAND_ALE (1 << 17) +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 + +/* + * FSMC NAND driver configuration + */ +#define CONFIG_SPEAR_FSMCBASE (0xD1800000) + +/* + * Command support defines + */ +/* #define CONFIG_CMD_CACHE */ +/* #define CONFIG_CMD_CDP */ +/* #define CONFIG_CMD_DHCP */ +#define CONFIG_CMD_I2C +/* #define CONFIG_CMD_ELF */ +/* #define CONFIG_CMD_PING */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_ENV +/* #define CONFIG_CMD_JFFS2 */ +/* #define CONFIG_CMD_YAFFS2 */ +#define CONFIG_CMD_MEMORY +/* #define CONFIG_CMD_MII */ +/* #define CONFIG_MII */ +/* #define CONFIG_NET_MULTI */ +/* #define CONFIG_CMD_NET */ +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_SETFREQ +/* #define CONFIG_CMD_EEPROM */ + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +/* + * Default Environment Varible definitions + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTARGS_NFS "root=/dev/nfs ip=dhcp " \ + "console=ttyS0 init=/bin/sh" + +/* #define CONFIG_ETHADDR 00:11:22:33:44:55 */ + +/* #define CONFIG_NETMASK 255.255.255.0 */ +/* #define CONFIG_IPADDR 192.168.1.10 */ +/* #define CONFIG_SERVERIP 192.168.1.1 */ +/* #define CONFIG_GATEWAYIP 192.168.1.1 */ +#define CONFIG_ENV_OVERWRITE + +/* + * U-Boot Environment placing definitions. + */ +#ifdef ENV_IN_NAND +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_FLASH +#endif + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_SYS_MONITOR_LEN 0x00040000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_ENV_SIZE 0x00002000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) + +#define CONFIG_BOOTARGS "console=ttyS0 mem=128M " \ + "root=/dev/mtdblock3 " \ + "rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND "bootm 0xf8050000" + +#else +#ifdef CONFIG_ENV_IS_IN_NAND + +#define CONFIG_ENV_OFFSET 0x50000 +#define CONFIG_ENV_SIZE 0x04000 +/* #define CONFIG_ENV_OFFSET_REDUND 0x58000 */ +#define CONFIG_ENV_RANGE 0x10000 + +#define CONFIG_BOOTARGS "console=ttyS0 mem=128M " \ + "root=/dev/mtdblock8 " \ + "rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \ + "0x60000 0x4C0000; " \ + "bootm 0x1600000" + +#endif +#endif + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_PROMPT \ + "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay + +#define CONFIG_SYS_MEMTEST_START 0x00800000 +#define CONFIG_SYS_MEMTEST_END 0x04000000 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "u-boot> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 +#define CONFIG_SYS_64BIT_VSPRINTF 1 + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) +#define CONFIG_STACKSIZE_FIQ (4*1024) +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_MAXSIZE 0x40000000 + +#endif /* __CONFIG_H */ +