On 07/09/2017 07:41 PM, Ran Wang wrote:
USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is ovserved, change set the same value.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com
arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++ arch/arm/cpu/armv7/ls102xa/soc.c | 14 ++++++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 ++++ 3 files changed, 24 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index b61f3cd..11e33d6 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -5,6 +5,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315
- select SYS_FSL_ERRATUM_A009008 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -50,6 +51,11 @@ config SECURE_BOOT config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315"
+config SYS_FSL_ERRATUM_A009008
- bool
- help
Workaround for USB erratum A009008- config SYS_FSL_SRDS_1 bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index b84a1a6..986337d 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -60,6 +60,17 @@ unsigned int get_soc_major_rev(void) return major; }
+static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
- u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
- u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
Put a blank here.
York