A previous patch below adding DDR mode support was actually for i.MX platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC, it uses different process for DDR mode. Let's drop DDR support code for i.MX in fsl_esdhc driver.
0e1bf61 mmc: fsl_esdhc: Add support for DDR mode
Signed-off-by: Yangbo Lu yangbo.lu@nxp.com --- Changes for v3: - Added this patch. --- drivers/mmc/fsl_esdhc.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 03a7e89..322046b 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -504,17 +504,16 @@ static void esdhc_set_clock(struct fsl_esdhc_priv *priv, struct mmc *mmc, struct fsl_esdhc *regs = priv->esdhc_regs; int div = 1; int pre_div = 2; - int ddr_pre_div = mmc->ddr_mode ? 2 : 1; int sdhc_clk = priv->sdhc_clk; uint clk;
if (clock < mmc->cfg->f_min) clock = mmc->cfg->f_min;
- while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) + while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256) pre_div *= 2;
- while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) + while (sdhc_clk / (div * pre_div) > clock && div < 16) div++;
pre_div >>= 1; @@ -699,10 +698,6 @@ static int fsl_esdhc_get_cfg(struct fsl_esdhc_priv *priv, else if (priv->bus_width == 4) cfg->host_caps = MMC_MODE_4BIT;
-#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE - cfg->host_caps |= MMC_MODE_DDR_52MHz; -#endif - if (caps & HOSTCAPBLT2_HSS) cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;