This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c. Merge the same code into a new file, memconf.c.
The helper functions no longer have to be placed in the header file. Also, move them into memconf.c.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---
Changes in v3: None Changes in v2: None
arch/arm/mach-uniphier/Makefile | 1 + arch/arm/mach-uniphier/include/mach/sg-regs.h | 119 +------------------------- arch/arm/mach-uniphier/memconf.c | 104 ++++++++++++++++++++++ arch/arm/mach-uniphier/ph1-ld4/sg_init.c | 11 +-- arch/arm/mach-uniphier/ph1-pro4/sg_init.c | 11 +-- arch/arm/mach-uniphier/spl.c | 11 ++- 6 files changed, 116 insertions(+), 141 deletions(-) create mode 100644 arch/arm/mach-uniphier/memconf.c
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index df418dd..e7a801b 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -7,6 +7,7 @@ ifdef CONFIG_SPL_BUILD obj-y += lowlevel_init.o obj-y += init_page_table.o obj-y += spl.o +obj-y += memconf.o obj-y += ddrphy_training.o
else diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/include/mach/sg-regs.h index 4ae67c8..63408d5 100644 --- a/arch/arm/mach-uniphier/include/mach/sg-regs.h +++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h @@ -1,7 +1,7 @@ /* * UniPhier SG (SoC Glue) block registers * - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -108,7 +108,6 @@ #else
#include <linux/types.h> -#include <linux/sizes.h> #include <asm/io.h>
static inline void sg_set_pinsel(int n, int value) @@ -117,122 +116,6 @@ static inline void sg_set_pinsel(int n, int value) | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n)); }
-static inline u32 sg_memconf_val_ch0(unsigned long size, int num) -{ - int size_mb = size / num; - u32 ret; - - switch (size_mb) { - case SZ_64M: - ret = SG_MEMCONF_CH0_SZ_64M; - break; - case SZ_128M: - ret = SG_MEMCONF_CH0_SZ_128M; - break; - case SZ_256M: - ret = SG_MEMCONF_CH0_SZ_256M; - break; - case SZ_512M: - ret = SG_MEMCONF_CH0_SZ_512M; - break; - case SZ_1G: - ret = SG_MEMCONF_CH0_SZ_1G; - break; - default: - BUG(); - break; - } - - switch (num) { - case 1: - ret |= SG_MEMCONF_CH0_NUM_1; - break; - case 2: - ret |= SG_MEMCONF_CH0_NUM_2; - break; - default: - BUG(); - break; - } - return ret; -} - -static inline u32 sg_memconf_val_ch1(unsigned long size, int num) -{ - int size_mb = size / num; - u32 ret; - - switch (size_mb) { - case SZ_64M: - ret = SG_MEMCONF_CH1_SZ_64M; - break; - case SZ_128M: - ret = SG_MEMCONF_CH1_SZ_128M; - break; - case SZ_256M: - ret = SG_MEMCONF_CH1_SZ_256M; - break; - case SZ_512M: - ret = SG_MEMCONF_CH1_SZ_512M; - break; - case SZ_1G: - ret = SG_MEMCONF_CH1_SZ_1G; - break; - default: - BUG(); - break; - } - - switch (num) { - case 1: - ret |= SG_MEMCONF_CH1_NUM_1; - break; - case 2: - ret |= SG_MEMCONF_CH1_NUM_2; - break; - default: - BUG(); - break; - } - return ret; -} - -static inline u32 sg_memconf_val_ch2(unsigned long size, int num) -{ - int size_mb = size / num; - u32 ret; - - switch (size_mb) { - case SZ_64M: - ret = SG_MEMCONF_CH2_SZ_64M; - break; - case SZ_128M: - ret = SG_MEMCONF_CH2_SZ_128M; - break; - case SZ_256M: - ret = SG_MEMCONF_CH2_SZ_256M; - break; - case SZ_512M: - ret = SG_MEMCONF_CH2_SZ_512M; - break; - default: - BUG(); - break; - } - - switch (num) { - case 1: - ret |= SG_MEMCONF_CH2_NUM_1; - break; - case 2: - ret |= SG_MEMCONF_CH2_NUM_2; - break; - default: - BUG(); - break; - } - return ret; -} #endif /* __ASSEMBLY__ */
#endif /* ARCH_SG_REGS_H */ diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c new file mode 100644 index 0000000..bf3c177 --- /dev/null +++ b/arch/arm/mach-uniphier/memconf.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada yamada.m@jp.panasonic.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/sizes.h> +#include <asm/io.h> +#include <mach/sg-regs.h> + +static inline u32 sg_memconf_val_ch0(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH0_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH0_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH0_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH0_SZ_512M; + break; + case SZ_1G: + ret = SG_MEMCONF_CH0_SZ_1G; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH0_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH0_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} + +static inline u32 sg_memconf_val_ch1(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH1_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH1_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH1_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH1_SZ_512M; + break; + case SZ_1G: + ret = SG_MEMCONF_CH1_SZ_1G; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH1_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH1_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} + +void memconf_init(void) +{ + u32 tmp; + + /* Set DDR size */ + tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); + tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); +#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE + tmp |= SG_MEMCONF_SPARSEMEM; +#endif + writel(tmp, SG_MEMCONF); +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/sg_init.c b/arch/arm/mach-uniphier/ph1-ld4/sg_init.c index e6bfa97..93e44af 100644 --- a/arch/arm/mach-uniphier/ph1-ld4/sg_init.c +++ b/arch/arm/mach-uniphier/ph1-ld4/sg_init.c @@ -1,11 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation * Author: Masahiro Yamada yamada.m@jp.panasonic.com * * SPDX-License-Identifier: GPL-2.0+ */
-#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h>
@@ -13,14 +12,6 @@ void sg_init(void) { u32 tmp;
- /* Set DDR size */ - tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); - tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); -#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE - tmp |= SG_MEMCONF_SPARSEMEM; -#endif - writel(tmp, SG_MEMCONF); - /* Input ports must be enabled before deasserting reset of cores */ tmp = readl(SG_IECTRL); tmp |= 0x1; diff --git a/arch/arm/mach-uniphier/ph1-pro4/sg_init.c b/arch/arm/mach-uniphier/ph1-pro4/sg_init.c index c25afa8..8677666 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/sg_init.c +++ b/arch/arm/mach-uniphier/ph1-pro4/sg_init.c @@ -1,11 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation * Author: Masahiro Yamada yamada.m@jp.panasonic.com * * SPDX-License-Identifier: GPL-2.0+ */
-#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h>
@@ -13,14 +12,6 @@ void sg_init(void) { u32 tmp;
- /* Set DDR size */ - tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); - tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); -#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE - tmp |= SG_MEMCONF_SPARSEMEM; -#endif - writel(tmp, SG_MEMCONF); - /* Input ports must be enabled before deasserting reset of cores */ tmp = readl(SG_IECTRL); tmp |= 1 << 6; diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c index c8a2469..c3d90d0 100644 --- a/arch/arm/mach-uniphier/spl.c +++ b/arch/arm/mach-uniphier/spl.c @@ -18,6 +18,7 @@ void sbc_init(void); void sg_init(void); void pll_init(void); void pin_init(void); +void memconf_init(void); void early_clkrst_init(void); int umc_init(void); void enable_dpll_ssc(void); @@ -38,10 +39,14 @@ void spl_board_init(void)
led_write(L, 0, , );
- early_clkrst_init(); + memconf_init();
led_write(L, 1, , );
+ early_clkrst_init(); + + led_write(L, 2, , ); + { int res;
@@ -51,9 +56,9 @@ void spl_board_init(void) ; } } - led_write(L, 2, , ); + led_write(L, 3, , );
enable_dpll_ssc();
- led_write(L, 3, , ); + led_write(L, 4, , ); }