KS2 ddr3 initialization uses ddr3_size global variable before u-boot relocation. Even if the variable is not being used after relocation, writing to it corrupts relocation table.
This patch removes the global ddr3_size variable and uses local one instead.
Signed-off-by: Vitaly Andrianov vitalya@ti.com --- arch/arm/cpu/armv7/keystone/ddr3.c | 5 +---- arch/arm/include/asm/arch-keystone/ddr3.h | 5 ++--- board/ti/ks2_evm/board.c | 6 ++++-- board/ti/ks2_evm/ddr3_k2e.c | 14 ++++++-------- board/ti/ks2_evm/ddr3_k2hk.c | 11 ++--------- board/ti/ks2_evm/ddr3_k2l.c | 12 ++---------- 6 files changed, 17 insertions(+), 36 deletions(-)
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c index 923906a..dfb27b5 100644 --- a/arch/arm/cpu/armv7/keystone/ddr3.c +++ b/arch/arm/cpu/armv7/keystone/ddr3.c @@ -263,17 +263,14 @@ static void ddr3_map_ecc_cic2_irq(u32 base) } #endif
-void ddr3_init_ecc(u32 base) +void ddr3_init_ecc(u32 base, u32 ddr3_size) { - u32 ddr3_size; - if (!ddr3_ecc_support_rmw(base)) { ddr3_disable_ecc(base); return; }
ddr3_ecc_init_range(base); - ddr3_size = ddr3_get_size(); ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
/* mapping DDR3 ECC system interrupt from CIC2 to GIC */ diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h index b044d6f..a22c237 100644 --- a/arch/arm/include/asm/arch-keystone/ddr3.h +++ b/arch/arm/include/asm/arch-keystone/ddr3.h @@ -48,10 +48,9 @@ struct ddr3_emif_config { unsigned int sdrfc; };
-void ddr3_init(void); -int ddr3_get_size(void); +u32 ddr3_init(void); void ddr3_reset_ddrphy(void); -void ddr3_init_ecc(u32 base); +void ddr3_init_ecc(u32 base, u32 ddr3_size); void ddr3_disable_ecc(u32 base); void ddr3_check_ecc_int(u32 base); int ddr3_ecc_support_rmw(u32 base); diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 04ec675..8892a28 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -35,12 +35,14 @@ static struct aemif_config aemif_configs[] = {
int dram_init(void) { - ddr3_init(); + u32 ddr3_size; + + ddr3_size = ddr3_init();
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); - ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE); + ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); return 0; }
diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c index 40fd966..35ffb42 100644 --- a/board/ti/ks2_evm/ddr3_k2e.c +++ b/board/ti/ks2_evm/ddr3_k2e.c @@ -11,11 +11,11 @@ #include "ddr3_cfg.h" #include <asm/arch/ddr3.h>
-static int ddr3_size; static struct pll_init_data ddr3_400 = DDR3_PLL_400;
-void ddr3_init(void) +u32 ddr3_init(void) { + u32 ddr3_size; char dimm_name[32];
if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1)) @@ -43,13 +43,11 @@ void ddr3_init(void) printf("DRAM: 4 GiB\n"); ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g); ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g); + } else { + printf("Unknown SO-DIMM. Cannot configure DDR3\n"); + while (1) + ; } -}
-/** - * ddr3_get_size - return ddr3 size in GiB - */ -int ddr3_get_size(void) -{ return ddr3_size; } diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c index a1c3d05..b36eb27 100644 --- a/board/ti/ks2_evm/ddr3_k2hk.c +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -12,14 +12,13 @@ #include <asm/arch/ddr3.h> #include <asm/arch/hardware.h>
-static int ddr3_size; - struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
-void ddr3_init(void) +u32 ddr3_init(void) { char dimm_name[32]; + u32 ddr3_size;
ddr3_get_dimm_params(dimm_name);
@@ -93,12 +92,6 @@ void ddr3_init(void) /* Apply the workaround for PG 1.0 and 1.1 Silicons */ if (cpu_revision() <= 1) ddr3_err_reset_workaround(); -}
-/** - * ddr3_get_size - return ddr3 size in GiB - */ -int ddr3_get_size(void) -{ return ddr3_size; } diff --git a/board/ti/ks2_evm/ddr3_k2l.c b/board/ti/ks2_evm/ddr3_k2l.c index 15a14f2..00fc194 100644 --- a/board/ti/ks2_evm/ddr3_k2l.c +++ b/board/ti/ks2_evm/ddr3_k2l.c @@ -11,28 +11,20 @@ #include "ddr3_cfg.h" #include <asm/arch/ddr3.h>
-static int ddr3_size; static struct pll_init_data ddr3_400 = DDR3_PLL_400;
-void ddr3_init(void) +u32 ddr3_init(void) { init_pll(&ddr3_400);
/* No SO-DIMM, 2GB discreet DDR */ printf("DRAM: 2 GiB\n"); - ddr3_size = 2;
/* Reset DDR3 PHY after PLL enabled */ ddr3_reset_ddrphy();
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g); ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g); -}
-/** - * ddr3_get_size - return ddr3 size in GiB - */ -int ddr3_get_size(void) -{ - return ddr3_size; + return 2; }