The MXC_*_UCTRL_*PM_BIT bits are available only on i.MX51.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Marek Vasut marex@denx.de Cc: Stefano Babic sbabic@denx.de --- .../drivers/usb/host/ehci-mx5.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c index bd1f119..8e42e56 100644 --- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c +++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c @@ -153,10 +153,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags) MXC_USB_PHY_CTR_FUNC_OFFSET);
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); +#ifdef CONFIG_MX51 if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_OTG_UCTRL_OPM_BIT; else v |= MXC_OTG_UCTRL_OPM_BIT; +#endif __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); } break; @@ -170,10 +172,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags) #endif
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); +#ifdef CONFIG_MX51 if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */ else v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */ +#endif __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); @@ -186,10 +190,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags) break; case 2: /* Host 2 ULPI */ v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); +#ifdef CONFIG_MX51 if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */ else v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */ +#endif
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); break;