Dear Kwon,
2023년 6월 28일 (수) 14:47, Hoegeun Kwon hoegeun.kwon@samsung.com님이 작성:
There is a problem that the rates of PLL0 and PLL1 are set incorrectly because the postdiv1_mask value is incorrectly entered when setting the pll clk reg. Modify postdiv1's mask value to be put correctly.
Signed-off-by: Hoegeun Kwon hoegeun.kwon@samsung.com
drivers/clk/starfive/clk-jh7110-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index 02e6d9000e29..7492b1f70dd4 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -185,7 +185,7 @@ static void jh7110_pll_set_rate(struct clk_jh7110_pllx *pll, PLLX_SET(pll->offset->dsmpd, pll->offset->dsmpd_mask, 1); PLLX_SET(pll->offset->prediv, pll->offset->prediv_mask, rate->prediv); PLLX_SET(pll->offset->fbdiv, pll->offset->fbdiv_mask, rate->fbdiv);
PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1, 0);
PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1_mask, 0); PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_ON); if (set) {-- 2.17.1
Reviewed-by: Minkyu Kang mk7.kang@samsung.com
Thanks.
--
Thanks. Minkyu Kang.