Re: [PATCH 1/4] ARM: dts: stm32: split sdram pin & timing parameter into specific board dts

25 Mar 2021

Hi Dillon
On 3/11/21 7:43 AM, dillon.minfei@gmail.com wrote:
...
From: dillon min dillon.minfei@gmail.com
As different boards has their own sdram hw connection, mount different
sdram modules, so move sdram timing parameter and pin configuration
to their board device tree.
Signed-off-by: dillon min dillon.minfei@gmail.com
arch/arm/dts/stm32h7-u-boot.dtsi          | 95 ------------------------------
 arch/arm/dts/stm32h743i-disco-u-boot.dtsi | 98 +++++++++++++++++++++++++++++++
 arch/arm/dts/stm32h743i-eval-u-boot.dtsi  | 98 +++++++++++++++++++++++++++++++
 3 files changed, 196 insertions(+), 95 deletions(-)

diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
index 54dd406..e34d066 100644
--- a/arch/arm/dts/stm32h7-u-boot.dtsi
+++ b/arch/arm/dts/stm32h7-u-boot.dtsi
@@ -36,30 +36,6 @@
   		pinctrl-0 = <&fmc_pins>;
   		pinctrl-names = "default";
   		status = "okay";


	/*


	 * Memory configuration from sdram datasheet IS42S32800G-6BLI


	 * first bank is bank@0


	 * second bank is bank@1


	 */


	bank1: bank@1 {


		st,sdram-control = /bits/ 8 <NO_COL_9


					     NO_ROW_12


					     MWIDTH_32


					     BANKS_4


					     CAS_2


					     SDCLK_3


					     RD_BURST_EN


					     RD_PIPE_DL_0>;


		st,sdram-timing = /bits/ 8 <TMRD_1


					    TXSR_1


					    TRAS_1


					    TRC_6


					    TRP_2


					    TWR_1


					    TRCD_1>;


		st,sdram-refcount = <1539>;


	};

};
};

};
@@ -136,77 +112,6 @@
   compatible = "st,stm32-gpio";
 };
-&pinctrl {

fmc_pins: fmc@0 {
pins {


	pinmux = <STM32_PINMUX('D', 0, AF12)>,


		 <STM32_PINMUX('D', 1, AF12)>,


		 <STM32_PINMUX('D', 8, AF12)>,


		 <STM32_PINMUX('D', 9, AF12)>,


		 <STM32_PINMUX('D',10, AF12)>,


		 <STM32_PINMUX('D',14, AF12)>,


		 <STM32_PINMUX('D',15, AF12)>,



		 <STM32_PINMUX('E', 0, AF12)>,


		 <STM32_PINMUX('E', 1, AF12)>,


		 <STM32_PINMUX('E', 7, AF12)>,


		 <STM32_PINMUX('E', 8, AF12)>,


		 <STM32_PINMUX('E', 9, AF12)>,


		 <STM32_PINMUX('E',10, AF12)>,


		 <STM32_PINMUX('E',11, AF12)>,


		 <STM32_PINMUX('E',12, AF12)>,


		 <STM32_PINMUX('E',13, AF12)>,


		 <STM32_PINMUX('E',14, AF12)>,


		 <STM32_PINMUX('E',15, AF12)>,



		 <STM32_PINMUX('F', 0, AF12)>,


		 <STM32_PINMUX('F', 1, AF12)>,


		 <STM32_PINMUX('F', 2, AF12)>,


		 <STM32_PINMUX('F', 3, AF12)>,


		 <STM32_PINMUX('F', 4, AF12)>,


		 <STM32_PINMUX('F', 5, AF12)>,


		 <STM32_PINMUX('F',11, AF12)>,


		 <STM32_PINMUX('F',12, AF12)>,


		 <STM32_PINMUX('F',13, AF12)>,


		 <STM32_PINMUX('F',14, AF12)>,


		 <STM32_PINMUX('F',15, AF12)>,



		 <STM32_PINMUX('G', 0, AF12)>,


		 <STM32_PINMUX('G', 1, AF12)>,


		 <STM32_PINMUX('G', 2, AF12)>,


		 <STM32_PINMUX('G', 4, AF12)>,


		 <STM32_PINMUX('G', 5, AF12)>,


		 <STM32_PINMUX('G', 8, AF12)>,


		 <STM32_PINMUX('G',15, AF12)>,



		 <STM32_PINMUX('H', 5, AF12)>,


		 <STM32_PINMUX('H', 6, AF12)>,


		 <STM32_PINMUX('H', 7, AF12)>,


		 <STM32_PINMUX('H', 8, AF12)>,


		 <STM32_PINMUX('H', 9, AF12)>,


		 <STM32_PINMUX('H',10, AF12)>,


		 <STM32_PINMUX('H',11, AF12)>,


		 <STM32_PINMUX('H',12, AF12)>,


		 <STM32_PINMUX('H',13, AF12)>,


		 <STM32_PINMUX('H',14, AF12)>,


		 <STM32_PINMUX('H',15, AF12)>,



		 <STM32_PINMUX('I', 0, AF12)>,


		 <STM32_PINMUX('I', 1, AF12)>,


		 <STM32_PINMUX('I', 2, AF12)>,


		 <STM32_PINMUX('I', 3, AF12)>,


		 <STM32_PINMUX('I', 4, AF12)>,


		 <STM32_PINMUX('I', 5, AF12)>,


		 <STM32_PINMUX('I', 6, AF12)>,


		 <STM32_PINMUX('I', 7, AF12)>,


		 <STM32_PINMUX('I', 9, AF12)>,


		 <STM32_PINMUX('I',10, AF12)>;



	slew-rate = <3>;


};


};

-};



&pwrcfg {
   u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
index 5965afc..02e28c6 100644
--- a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
@@ -1,3 +1,101 @@
 // SPDX-License-Identifier: GPL-2.0+
#include <stm32h7-u-boot.dtsi>



+&fmc {


/*
* Memory configuration from sdram datasheet IS42S32800G-6BLI


* first bank is bank@0


* second bank is bank@1


*/


bank1: bank@1 {
st,sdram-control = /bits/ 8 <NO_COL_9


			     NO_ROW_12


			     MWIDTH_32


			     BANKS_4


			     CAS_2


			     SDCLK_3


			     RD_BURST_EN


			     RD_PIPE_DL_0>;


st,sdram-timing = /bits/ 8 <TMRD_1


			    TXSR_1


			    TRAS_1


			    TRC_6


			    TRP_2


			    TWR_1


			    TRCD_1>;


st,sdram-refcount = <1539>;


};

+};



+&pinctrl {

fmc_pins: fmc@0 {
pins {


	pinmux = <STM32_PINMUX('D', 0, AF12)>,


		 <STM32_PINMUX('D', 1, AF12)>,


		 <STM32_PINMUX('D', 8, AF12)>,


		 <STM32_PINMUX('D', 9, AF12)>,


		 <STM32_PINMUX('D',10, AF12)>,


		 <STM32_PINMUX('D',14, AF12)>,


		 <STM32_PINMUX('D',15, AF12)>,



		 <STM32_PINMUX('E', 0, AF12)>,


		 <STM32_PINMUX('E', 1, AF12)>,


		 <STM32_PINMUX('E', 7, AF12)>,


		 <STM32_PINMUX('E', 8, AF12)>,


		 <STM32_PINMUX('E', 9, AF12)>,


		 <STM32_PINMUX('E',10, AF12)>,


		 <STM32_PINMUX('E',11, AF12)>,


		 <STM32_PINMUX('E',12, AF12)>,


		 <STM32_PINMUX('E',13, AF12)>,


		 <STM32_PINMUX('E',14, AF12)>,


		 <STM32_PINMUX('E',15, AF12)>,



		 <STM32_PINMUX('F', 0, AF12)>,


		 <STM32_PINMUX('F', 1, AF12)>,


		 <STM32_PINMUX('F', 2, AF12)>,


		 <STM32_PINMUX('F', 3, AF12)>,


		 <STM32_PINMUX('F', 4, AF12)>,


		 <STM32_PINMUX('F', 5, AF12)>,


		 <STM32_PINMUX('F',11, AF12)>,


		 <STM32_PINMUX('F',12, AF12)>,


		 <STM32_PINMUX('F',13, AF12)>,


		 <STM32_PINMUX('F',14, AF12)>,


		 <STM32_PINMUX('F',15, AF12)>,



		 <STM32_PINMUX('G', 0, AF12)>,


		 <STM32_PINMUX('G', 1, AF12)>,


		 <STM32_PINMUX('G', 2, AF12)>,


		 <STM32_PINMUX('G', 4, AF12)>,


		 <STM32_PINMUX('G', 5, AF12)>,


		 <STM32_PINMUX('G', 8, AF12)>,


		 <STM32_PINMUX('G',15, AF12)>,



		 <STM32_PINMUX('H', 5, AF12)>,


		 <STM32_PINMUX('H', 6, AF12)>,


		 <STM32_PINMUX('H', 7, AF12)>,


		 <STM32_PINMUX('H', 8, AF12)>,


		 <STM32_PINMUX('H', 9, AF12)>,


		 <STM32_PINMUX('H',10, AF12)>,


		 <STM32_PINMUX('H',11, AF12)>,


		 <STM32_PINMUX('H',12, AF12)>,


		 <STM32_PINMUX('H',13, AF12)>,


		 <STM32_PINMUX('H',14, AF12)>,


		 <STM32_PINMUX('H',15, AF12)>,



		 <STM32_PINMUX('I', 0, AF12)>,


		 <STM32_PINMUX('I', 1, AF12)>,


		 <STM32_PINMUX('I', 2, AF12)>,


		 <STM32_PINMUX('I', 3, AF12)>,


		 <STM32_PINMUX('I', 4, AF12)>,


		 <STM32_PINMUX('I', 5, AF12)>,


		 <STM32_PINMUX('I', 6, AF12)>,


		 <STM32_PINMUX('I', 7, AF12)>,


		 <STM32_PINMUX('I', 9, AF12)>,


		 <STM32_PINMUX('I',10, AF12)>;



	slew-rate = <3>;


};


};

+};
diff --git a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
index 5965afc..02e28c6 100644
--- a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
+++ b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
@@ -1,3 +1,101 @@
 // SPDX-License-Identifier: GPL-2.0+
#include <stm32h7-u-boot.dtsi>



+&fmc {


/*
* Memory configuration from sdram datasheet IS42S32800G-6BLI


* first bank is bank@0


* second bank is bank@1


*/


bank1: bank@1 {
st,sdram-control = /bits/ 8 <NO_COL_9


			     NO_ROW_12


			     MWIDTH_32


			     BANKS_4


			     CAS_2


			     SDCLK_3


			     RD_BURST_EN


			     RD_PIPE_DL_0>;


st,sdram-timing = /bits/ 8 <TMRD_1


			    TXSR_1


			    TRAS_1


			    TRC_6


			    TRP_2


			    TWR_1


			    TRCD_1>;


st,sdram-refcount = <1539>;


};

+};



+&pinctrl {

fmc_pins: fmc@0 {
pins {


	pinmux = <STM32_PINMUX('D', 0, AF12)>,


		 <STM32_PINMUX('D', 1, AF12)>,


		 <STM32_PINMUX('D', 8, AF12)>,


		 <STM32_PINMUX('D', 9, AF12)>,


		 <STM32_PINMUX('D',10, AF12)>,


		 <STM32_PINMUX('D',14, AF12)>,


		 <STM32_PINMUX('D',15, AF12)>,



		 <STM32_PINMUX('E', 0, AF12)>,


		 <STM32_PINMUX('E', 1, AF12)>,


		 <STM32_PINMUX('E', 7, AF12)>,


		 <STM32_PINMUX('E', 8, AF12)>,


		 <STM32_PINMUX('E', 9, AF12)>,


		 <STM32_PINMUX('E',10, AF12)>,


		 <STM32_PINMUX('E',11, AF12)>,


		 <STM32_PINMUX('E',12, AF12)>,


		 <STM32_PINMUX('E',13, AF12)>,


		 <STM32_PINMUX('E',14, AF12)>,


		 <STM32_PINMUX('E',15, AF12)>,



		 <STM32_PINMUX('F', 0, AF12)>,


		 <STM32_PINMUX('F', 1, AF12)>,


		 <STM32_PINMUX('F', 2, AF12)>,


		 <STM32_PINMUX('F', 3, AF12)>,


		 <STM32_PINMUX('F', 4, AF12)>,


		 <STM32_PINMUX('F', 5, AF12)>,


		 <STM32_PINMUX('F',11, AF12)>,


		 <STM32_PINMUX('F',12, AF12)>,


		 <STM32_PINMUX('F',13, AF12)>,


		 <STM32_PINMUX('F',14, AF12)>,


		 <STM32_PINMUX('F',15, AF12)>,



		 <STM32_PINMUX('G', 0, AF12)>,


		 <STM32_PINMUX('G', 1, AF12)>,


		 <STM32_PINMUX('G', 2, AF12)>,


		 <STM32_PINMUX('G', 4, AF12)>,


		 <STM32_PINMUX('G', 5, AF12)>,


		 <STM32_PINMUX('G', 8, AF12)>,


		 <STM32_PINMUX('G',15, AF12)>,



		 <STM32_PINMUX('H', 5, AF12)>,


		 <STM32_PINMUX('H', 6, AF12)>,


		 <STM32_PINMUX('H', 7, AF12)>,


		 <STM32_PINMUX('H', 8, AF12)>,


		 <STM32_PINMUX('H', 9, AF12)>,


		 <STM32_PINMUX('H',10, AF12)>,


		 <STM32_PINMUX('H',11, AF12)>,


		 <STM32_PINMUX('H',12, AF12)>,


		 <STM32_PINMUX('H',13, AF12)>,


		 <STM32_PINMUX('H',14, AF12)>,


		 <STM32_PINMUX('H',15, AF12)>,



		 <STM32_PINMUX('I', 0, AF12)>,


		 <STM32_PINMUX('I', 1, AF12)>,


		 <STM32_PINMUX('I', 2, AF12)>,


		 <STM32_PINMUX('I', 3, AF12)>,


		 <STM32_PINMUX('I', 4, AF12)>,


		 <STM32_PINMUX('I', 5, AF12)>,


		 <STM32_PINMUX('I', 6, AF12)>,


		 <STM32_PINMUX('I', 7, AF12)>,


		 <STM32_PINMUX('I', 9, AF12)>,


		 <STM32_PINMUX('I',10, AF12)>;



	slew-rate = <3>;


};


};

+};
Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com
Thanks
Patrice

    

Re: [PATCH 1/4] ARM: dts: stm32: split sdram pin & timing parameter into specific board dts

Patrice CHOTARD

Signed-off-by: dillon min dillon.minfei@gmail.com