Dear Gabriel Huau,
Signed-off-by: Gabriel Huau contact@huau-gabriel.fr
Changes for v2:
- Coding style cleanup
- Remove unnecessary files modification
- Remove unnecessary board configuration set
Changes for v3:
- Coding style cleanup
- Move some macro definition from lowlevel_init.S to a new header
- Remove some "magic bloat" with I/O board initialization
- Add a pll_delay and replace loop by it
- Somme cleanup in the configuration file
- Cancel modifications on an SoC specific header
- Add my name to copyright
Changes for v4:
- Move dram init to dram_init() instead low_levelinit
- Remove u -boot env from configuration file and change the address of initial SP
- Remove PLL init, now it's SoC specific
Changes for v5:
- Clean up configuration file
- Add a MAINTAINERS entry
- Add a README.mini2440 file
- Use gpio/iomux interface in case of magic numbers
- Use get_ram_size()
Changes for v6:
- Coding style cleanup
- Remove some unused define in the board config
Changes for v7:
- Cleanup coding style
- Changement of the commit message
MAINTAINERS | 4 + board/friendlyarm/mini2440/Makefile | 44 ++++++++ board/friendlyarm/mini2440/mini2440.c | 134 ++++++++++++++++++++++++ board/friendlyarm/mini2440/mini2440.h | 144 +++++++++++++++++++++++++ boards.cfg | 1 + doc/README.mini2440 | 28 +++++ include/configs/mini2440.h | 186 +++++++++++++++++++++++++++++++++ 7 files changed, 541 insertions(+) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 doc/README.mini2440 create mode 100644 include/configs/mini2440.h
diff --git a/MAINTAINERS b/MAINTAINERS index 708ded7..2611fb5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -566,6 +566,10 @@ Unknown / orphaned boards: # Board CPU # #########################################################################
+Gabriel HUAU contact@huau-gabriel.fr
- mini2440 s3c2440
Albert ARIBAUD albert.u.boot@aribaud.net
edminiv2 ARM926EJS (Orion5x SoC) diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile new file mode 100644 index 0000000..b88e569 --- /dev/null +++ b/board/friendlyarm/mini2440/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2012 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +#
+include $(TOPDIR)/config.mk
+LIB = $(obj)lib$(BOARD).o
+COBJS := mini2440.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS))
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+#########################################################################
+# defines $(obj).depend target +include $(SRCTREE)/rules.mk
+sinclude $(obj).depend
+######################################################################### diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c new file mode 100644 index 0000000..e97d981 --- /dev/null +++ b/board/friendlyarm/mini2440/mini2440.c @@ -0,0 +1,134 @@ +/*
- (C) Copyright 2002
- Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- Marius Groeger mgroeger@sysgo.de
- (C) Copyright 2002
- David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- (C) Copyright 2009
- Michel Pollet buserror@gmail.com
- (C) Copyright 2012
- Gabriel Huau contact@huau-gabriel.fr
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <asm/arch/s3c2440.h> +#include <asm/arch/iomux.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <netdev.h> +#include "mini2440.h"
+DECLARE_GLOBAL_DATA_PTR;
+static inline void pll_delay(unsigned long loops) +{
- __asm__ volatile ("1:\n"
"subs %0, %1, #1\n""bne 1b" : "=r" (loops) : "0" (loops));+}
+int board_early_init_f(void) +{
- struct s3c24x0_clock_power * const clk_power =
s3c24x0_get_base_clock_power();- /* to reduce PLL lock time, adjust the LOCKTIME register */
- clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
- clk_power->clkdivn = CLKDIVN_VAL;
- /* configure UPLL */
- clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
- /* some delay between MPLL and UPLL */
- pll_delay(100);
- /* configure MPLL */
- clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
- /* some delay between MPLL and UPLL */
- pll_delay(10000);
- return 0;
+}
+/*
- Miscellaneous platform dependent initialisations
- */
+int board_init(void) +{
- struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- /* IOMUX Port H : UART Configuration */
- gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;- gpio_direction_output(GPH8, 0);
- gpio_direction_output(GPH9, 0);
- gpio_direction_output(GPH10, 0);
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
- return 0;
+}
+int dram_init(void) +{
- struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
- /*
* Configuring bus width and timing* Initialize clocks for each bank 0..5* Bank 3 and 4 are used for DM9000*/- writel(BANK_CONF, &memctl->bwscon);
- writel(B0_CONF, &memctl->bankcon[0]);
- writel(B1_CONF, &memctl->bankcon[1]);
- writel(B2_CONF, &memctl->bankcon[2]);
- writel(B3_CONF, &memctl->bankcon[3]);
- writel(B4_CONF, &memctl->bankcon[4]);
- writel(B5_CONF, &memctl->bankcon[5]);
- /* Bank 6 and 7 are used for DRAM */
- writel(SDRAM_64MB, &memctl->bankcon[6]);
- writel(SDRAM_64MB, &memctl->bankcon[7]);
- writel(MEM_TIMING, &memctl->refresh);
- writel(BANKSIZE_CONF, &memctl->banksize);
- writel(B6_MRSR, &memctl->mrsrb6);
- writel(B7_MRSR, &memctl->mrsrb7);
- gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_SIZE);- return 0;
+}
+int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_DRIVER_DM9000
- return dm9000_initialize(bis);
+#else
- return 0;
+#endif +} diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h new file mode 100644 index 0000000..db386ea --- /dev/null +++ b/board/friendlyarm/mini2440/mini2440.h @@ -0,0 +1,144 @@ +#ifndef __MINI2440_BOARD_CONF_H__ +#define __MINI2440_BOARD_CONF_H__
+/* PLL Parameters */ +#define CLKDIVN_VAL 7 +#define M_MDIV 0x7f +#define M_PDIV 0x2 +#define M_SDIV 0x1
+#define U_M_MDIV 0x38 +#define U_M_PDIV 0x2 +#define U_M_SDIV 0x2
+/* BWSCON */ +#define DW8 0x0 +#define DW16 0x1 +#define DW32 0x2 +#define WAIT (0x1<<2) +#define UBLB (0x1<<3)
+#define B1_BWSCON (DW32) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16 + WAIT + UBLB) +#define B4_BWSCON (DW16 + WAIT + UBLB) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32)
+/*
- Bank Configuration
- */
+#define B0_Tacs 0x0 /* 0clk */ +#define B0_Tcos 0x0 /* 0clk */ +#define B0_Tacc 0x7 /* 14clk */ +#define B0_Tcoh 0x0 /* 0clk */ +#define B0_Tah 0x0 /* 0clk */ +#define B0_Tacp 0x0 /* 0clk */ +#define B0_PMC 0x0 /* normal */
+#define B1_Tacs 0x0 +#define B1_Tcos 0x0 +#define B1_Tacc 0x7 +#define B1_Tcoh 0x0 +#define B1_Tah 0x0 +#define B1_Tacp 0x0 +#define B1_PMC 0x0
+#define B2_Tacs 0x0 +#define B2_Tcos 0x0 +#define B2_Tacc 0x7 +#define B2_Tcoh 0x0 +#define B2_Tah 0x0 +#define B2_Tacp 0x0 +#define B2_PMC 0x0
+#define B3_Tacs 0x0 +#define B3_Tcos 0x3 /* 4clk */ +#define B3_Tacc 0x7 +#define B3_Tcoh 0x1 /* 1clk */ +#define B3_Tah 0x3 /* 4clk */ +#define B3_Tacp 0x0 +#define B3_PMC 0x0
+#define B4_Tacs 0x0 +#define B4_Tcos 0x3 +#define B4_Tacc 0x7 +#define B4_Tcoh 0x1 +#define B4_Tah 0x3 +#define B4_Tacp 0x0 +#define B4_PMC 0x0
+#define B5_Tacs 0x0 +#define B5_Tcos 0x0 +#define B5_Tacc 0x7 +#define B5_Tcoh 0x0 +#define B5_Tah 0x0 +#define B5_Tacp 0x0 +#define B5_PMC 0x0
+/*
- SDRAM Configuration
- */
+#define SDRAM_MT 0x3 /* SDRAM */ +#define SDRAM_Trcd 0x0 /* 2clk */ +#define SDRAM_SCAN_9 0x1 /* 9bit */ +#define SDRAM_SCAN_10 0x2 /* 10bit */
+#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
+/*
- Refresh Parameter
- */
+#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define Trp 0x1 /* 3clk */ +#define Trc 0x3 /* 7clk */ +#define Tchr 0x0 /* unused */ +#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 +
1-10.37*100)
*/ + +/*
- MRSR Parameter
- */
+#define BL 0x0 +#define BT 0x0 +#define CL 0x3 /* 3 clocks */ +#define TM 0x0 +#define WBL 0x0
+/*
- BankSize Parameter
- */
+#define BK76MAP 0x2 /* 128MB/128MB */ +#define SCLK_EN 0x1 /* SCLK active */ +#define SCKE_EN 0x1 /* SDRAM power down mode enable */ +#define BURST_EN 0x1 /* Burst enable */
+/*
- Register values
- */
+#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12)
- \ + (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
(B7_BWSCON<<28)))+#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
(B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))+#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
(B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))+#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
(B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))+#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
(B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))+#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
(B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))+#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
(B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))+#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
- (Trc<<18) + (Tchr<<16) + REFCNT
+#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7) +#define B6_MRSR (CL<<4) +#define B7_MRSR (CL<<4)
+#endif diff --git a/boards.cfg b/boards.cfg index 3cf75c3..93eeb3c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -61,6 +61,7 @@ mx1ads arm arm920t - - scb9328 arm arm920t - - imx cm4008 arm arm920t - - ks8695 cm41xx arm arm920t - - ks8695 +mini2440 arm arm920t mini2440 friendlyarm s3c24x0 VCMA9 arm arm920t vcma9 mpl s3c24x0 smdk2410 arm arm920t - samsung s3c24x0 omap1510inn arm arm925t - ti diff --git a/doc/README.mini2440 b/doc/README.mini2440 new file mode 100644 index 0000000..311ca52 --- /dev/null +++ b/doc/README.mini2440 @@ -0,0 +1,28 @@ +U-Boot for FriendlyARM Mini2440 (s3c2440)
+This file contains information for the port of U-Boot to FriendlyARM +mini2440
+All information about the board can be found on : +http://www.friendlyarm.net/products/mini2440
+To build u-boot : ./MAKEALL mini2440
+Overview : +-------- +FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440 +ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9 +systems. It's a low cost board.
+Boot Methods : +------------ +Mini2440 can boot from NOR or NAND.
+Build : +----- +./MAKEALL mini2440
+or
+make mini2440_config +make diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h new file mode 100644 index 0000000..fa7987c --- /dev/null +++ b/include/configs/mini2440.h @@ -0,0 +1,186 @@ +/*
- (C) Copyright 2002
- Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- Marius Groeger mgroeger@sysgo.de
- Gary Jennejohn gj@denx.de
- David Mueller d.mueller@elsoft.ch
- (C) Copyright 2009-2010
- Michel Pollet buserror@gmail.com
- (C) Copyright 2012
- Gabriel Huau contact@huau-gabriel.fr
- Configuation settings for the MINI2440 board.
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+#define CONFIG_SYS_TEXT_BASE 0x0 +#define CONFIG_S3C2440_GPIO
+/*
- High Level Configuration Options
- */
+#define CONFIG_ARM920T /* This is an ARM920T Core
*/
+#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */ +#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */ +#define CONFIG_MINI2440 /* on a MIN2440 Board */
+#define MACH_TYPE_MINI2440 1999 +#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
+/*
- We don't use lowlevel_init
- */
+#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F
+/*
- input clock of PLL
- */
+/* MINI2440 has 12.0000MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 12000000
+/*
- Size of malloc() pool
- */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
+/*
- Hardware drivers
- */
+#define CONFIG_DRIVER_DM9000 +#define CONFIG_DRIVER_DM9000_NO_EEPROM +#define CONFIG_DM9000_BASE 0x20000300 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+4)
+/*
- select serial console configuration
- */
+#define CONFIG_S3C24X0_SERIAL +#define CONFIG_SERIAL1
+/*
- allow to overwrite serial and ethaddr
- */
+#define CONFIG_ENV_OVERWRITE
+/*
- Command definition
- */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PORTIO +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SAVES
+/*
- Miscellaneous configurable options
- */
+#define CONFIG_LONGHELP +#define CONFIG_SYS_PROMPT "MINI2440 => " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define[tab] mixed with #define[space] ... also, please Cc Albert Aribaud for the next round, he'll likely pick this up.
+#define CONFIG_SYS_MEMTEST_START 0x30000000 +#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM
*/
+/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x32000000
+/* boot parameters address */ +#define CONFIG_BOOT_PARAM_ADDR 0x30000100
+/*
- the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
- it to wrap 100 times (total 1562500) to get 1 sec.
- */
+#define CONFIG_SYS_HZ 1562500
+/*
- valid baudrates
- */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_BAUDRATE 115200
+/*
- Stack sizes
- The stack sizes are set up in start.S using the settings below
- */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif
+/*
- Physical Memory Map
- */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x30000000 +#define CONFIG_SYS_FLASH_BASE 0x0
+/*
- Stack should be on the SRAM because
- DRAM is not init
- */
+#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 -
GENERATED_GBL_DATA_SIZE)
+/*
- NOR FLASH organization
- Now uses the standard CFI interface
- FLASH and environment organization
- */
+#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MONITOR_BASE 0x0 +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* 512 * 4096 sectors, or 32 * 64k blocks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#define CONFIG_FLASH_SHOW_PROGRESS 1
+/*
- Config for NOR flash
- */
+#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_MY_ENV_OFFSET 0x40000 +/* addr of environment */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE +
CONFIG_MY_ENV_OFFSET)
+/* 16k Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE 0x4000
+/* ATAG configuration */ +#define CONFIG_INITRD_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE
+#endif /* __CONFIG_H */