Update misc SOC related settings for i.MX6ULL, such as FEC mac address, cpu speed grading and mmdc channel mask clearing.
Also update s_init to skip pfd reset.
Signed-off-by: Peng Fan peng.fan@nxp.com Cc: Stefano Babic sbabic@denx.de --- arch/arm/cpu/armv7/mx6/soc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 4083ba5..f062d86 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -126,7 +126,7 @@ u32 get_cpu_speed_grade_hz(void) val >>= OCOTP_CFG3_SPEED_SHIFT; val &= 0x3;
- if (is_mx6ul()) { + if (is_mx6ul() || is_mx6ull()) { if (val == OCOTP_CFG3_SPEED_528MHZ) return 528000000; else if (val == OCOTP_CFG3_SPEED_696MHZ) @@ -293,7 +293,7 @@ static void clear_mmdc_ch_mask(void) reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */ - if (is_mx6sx() || is_mx6ul() || is_mx6sl()) + if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); else reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); @@ -459,7 +459,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) struct fuse_bank4_regs *fuse = (struct fuse_bank4_regs *)bank->fuse_regs;
- if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) { + if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) { u32 value = readl(&fuse->mac_addr2); mac[0] = value >> 24 ; mac[1] = value >> 16 ; @@ -523,7 +523,7 @@ void s_init(void) u32 mask528; u32 reg, periph1, periph2;
- if (is_mx6sx() || is_mx6ul()) + if (is_mx6sx() || is_mx6ul() || is_mx6ull()) return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs